DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 4-6 and 12-15 are objected to because of the following informalities:
In claim 4, line 1, substitute “Claim 1” with --Claim 2-- (changing dependency since “the two first source lines” in claim 4 is introduced in claim 2 for the first time).
In claim 12, line 11, substitute “the” with --a-- before “first horizontal direction.”
In claim 12, line 12, substitute “source” with --surface-- after “a bottom.”
Claims 5, 6 and 13-15 variously depend from claim 4 or 12, so they are objected for the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 10-14 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US Pub. 2021/0159275; hereinafter “Cheng”).
Regarding Claim 1, Cheng discloses a memory device comprising: an array of access transistors T located on a semiconductor substrate 100 (page 2, paragraph 16; see fig. 4); metal interconnect structures (M1-M-3, V1-V3) formed within dielectric material layers (ILD not shown; page 2, paragraph 18) and electrically connected to electrical nodes (connections between conductive plugs CP and S/D regions of the transistors T; see fig. 4) of each of the array of access transistors T (see fig. 4); and an array of resistive memory structures MU (page 3, paragraph 25-page 4, paragraph 26) located within the dielectric material layers and electrically connected to a respective one of the access transistors T (see fig. 4), wherein the metal interconnect structures (M1-M3, V1-V3) comprise: at least one first source line SL (page 2, paragraph 18) located at a first metal line level (M1 level) that is vertically spaced from a top surface of the semiconductor substrate 100 by a first vertical spacing (see fig. 2B) and laterally extending along a first horizontal direction D1 (the first source line SL has a width dimension extending along the horizontal direction D1; see figs. 2B and 4); a second source line M3 (page 4, paragraph 29) located at a second metal line level (M3 level) that is vertically spaced from the top surface of the semiconductor substrate 100 by a second vertical spacing (see fig. 4) that is different from the first vertical spacing and laterally extending along the first horizontal direction D1 (the second source line M3 has a length dimension extending along the horizontal direction D1; see fig. 4); and a vertical connection structure (M2, V1-V3) comprising a plurality of interconnection via structures (V1-V3) and at least one line-level metal structure M2 (see fig. 4) and providing a vertical electrical connection between the at least one first source line SL and the second source line M3 (see fig. 4).
Regarding Claim 2, Cheng discloses wherein: the at least one first source line SL comprises two first source lines SL (see figs. 2B and 4); and the vertical connection structure (M2, V1-V3) continuously extends from top surfaces of the two first source lines to a bottom surface of the second source line M3 (see fig. 4).
Regarding Claim 3, Cheng discloses wherein: the array of resistive memory structures MU is located within a memory array region in a plan view (regions where the resistive memory structures MU are formed; see figs. 2H and 4); and the vertical connection structure (M2, V1-V3) is located within a vertical connection region (regions between the resistive memory structures regions; see figs. 2H and 4) that is laterally offset from the memory array region in the plan view (see figs. 2H and 4).
Regarding Claim 4, Cheng discloses wherein the two first source lines SL laterally extend over a column of access transistors T (a column of transistors T oriented in the direction D1 or D2; see fig. 4) within the array of access transistors T that comprises a set of N access transistors T (showing at least 4 transistors; see fig. 2B), and are electrically connected to each source region S within the set of N access transistors T, N being an integer greater than 1 (see fig. 2B).
Regarding Claim 5, Cheng discloses further comprising two columns of source contact via structures CP (page 2, paragraph 17) arranged along the first horizontal direction D1, wherein each source contact via structure CP contacts a bottom surface of a respective one of the two first source lines SL and contacts a top surface of a source region S of a respective access transistor T within the column of access transistors T (see fig. 2B).
Regarding Claim 6, Cheng discloses wherein each source region S within the column of access transistors T is contacted by a respective first source contact via structure CP that contacts a bottom surface of one of the two first source lines SL (see fig. 2B) and by a respective second source contact via structure CP that contacts a bottom surface of another of the two first source lines SL (see fig. 2B).
Regarding Claim 10, Cheng discloses further comprising a bit line BL (page 4, paragraph 27) that overlies a horizontal plane including top surfaces of each of the array of resistive memory structures MU (see figs. 2I and 4) and electrically connected to top electrodes TE (page 3, paragraph 25) of a column of resistive memory structures MU (a column of resistive memory structures MU oriented in the direction D1 or D2; see figs. 2H and 4) within the array of resistive memory structures MU (see fig. 4), wherein the second source line M3 overlies the bit line BL (see fig. 4).
Regarding Claim 11, Cheng discloses wherein the second source line M3 has an areal overlap with each of the two first source lines SL in a plan view (see fig. 4).
Regarding Claim 12, Cheng discloses a memory device comprising: a column of access transistors T located on a semiconductor substrate 100 (page 2, paragraph 16; see fig. 4) and arranged along a first horizontal direction D1 (see fig. 4); metal interconnect structures (M1-M-3, V1-V3) embedded in dielectric material layers (ILD not shown; page 2, paragraph 18) and electrical connected to electrical nodes (connections between conductive plugs CP and S/D regions of the transistors T; see fig. 4) of each of the column of access transistors T (see fig. 4); and a column of resistive memory structures MU (page 3, paragraph 25-page 4, paragraph 26) formed within the dielectric material layers (see fig. 4), wherein the metal interconnect structures (M1-M-3, V1-V3) comprise: two first source lines SL (page 2, paragraph 18; see fig. 2B) located at a first metal line level (M1 level) that is vertically spaced from a top surface of the semiconductor substrate 100 by a first vertical spacing (see fig. 2B) and laterally extending along the first horizontal direction D1 (each of the two first source lines SL has a width dimension extending along the horizontal direction D1; see figs. 2B and 4); first source contact via structures CP (page 2, paragraph 17) located on a bottom surface of one of the two first source lines SL (see figs. 2B and 4); and second source contact via structures CP located on a bottom surface of another of the two first source lines SL (see figs. 2B and 4), wherein each source region S within the column of access transistors T is located on a respective one of the first source contact via structures CP and on a respective one of the second source contact via structures CP (see figs. 2B and 4).
Regarding Claim 13, Cheng discloses wherein the metal interconnect structures (M1-M-3, V1-V3) comprise: a second source line M3 (page 4, paragraph 29) located at a second metal line level (M3 level) that is vertically spaced from the top surface of the semiconductor substrate 100 by a second vertical spacing (see fig. 4) that is different from the first vertical spacing and laterally extending along the first horizontal direction D1 (the second source line M3 has a length dimension extending along the first horizontal direction D1; see fig. 4); and a vertical connection structure (M2, V1-V3) comprising a plurality of interconnection via structures (V1-V3) and at least one line-level metal structure M2 (see fig. 4) and providing a vertical electrical connection between the two first source lines SL and the second source line M3 (see fig. 4).
Regarding Claim 14, Cheng discloses further comprising a bit line BL (page 4, paragraph 27) that overlies a horizontal plane including top surfaces of the column of resistive memory structures MU (see figs. 2I and 4) and electrically connected to top electrodes TE (page 3, paragraph 25) of the column of resistive memory structures MU (see figs. 2H and 4), wherein the second source line M3 overlies the bit line BL (see fig. 4).
Regarding Claim 16, Cheng discloses a method of forming a memory device, the method comprising: forming a column of access transistors T arranged along a first horizontal direction D2 on a semiconductor substrate 100 (page 2, paragraph 16; see fig. 4); forming lower-level metal interconnect structures (CP, M1, V1) formed within lower-level dielectric material layers (ILD not shown; page 2, paragraph 18) over the column of access transistors T (see fig. 2B), wherein the lower-level metal interconnect structures (CP, M1, V1) comprise two first source lines SL (page 2, paragraph 18) located at a first metal line level (M1 level) that is vertically spaced from a top surface of the semiconductor substrate 100 by a first vertical spacing (see fig. 2B) and laterally extending along the first horizontal direction D2 (each of the two first source lines SL has a length dimension extending along the horizontal direction D2) and laterally spaced from each other along a second horizontal direction D1 (see fig. 2B), wherein each source region S within the column of access transistors T is electrically connected to each of the two first source lines SL (see figs. 2B and 4); forming a column of resistive memory structures MU (page 3, paragraph 25-page , paragraph 26), wherein each resistive memory structure MU within the column of resistive memory structures MU is electrically connected to a drain region D of a respective access transistor T within the column of access transistors T (see fig. 2H); and forming upper-level metal interconnect structures (M2, V2, M3) formed within upper-level dielectric material layers (ILD not shown; page 4, paragraphs 27 and 29; see fig. 2J), wherein the upper-level metal interconnect structures (M2, V2, M3) comprise a second source line M3 (page 4, paragraph 29) located at a second metal line level (M3 level) that is vertically spaced from the top surface of the semiconductor substrate 100 by a second vertical spacing that is different from the first vertical spacing (see fig. 2J) and laterally extending along the first horizontal direction D2 (the second source line M3 has a width dimension extending along the horizontal direction D2; see fig. 2J) and electrically connected to each of the two first source lines SL (see figs. 2J and 4).
Regarding Claim 17, Cheng discloses further comprising forming a vertical connection structure (M2, V1-V3) vertically connecting the two first source lines SL and the second source line M3 (see fig. 2J), wherein the vertical connection structure (M2, V1-V3) comprises a plurality of interconnection via structures (V1-V3) and at least one line-level metal structure M2 (see fig. 2J).
Regarding Claim 18, Cheng discloses wherein: the column of access transistors T is formed within a memory array region (regions where the resistive memory structures MU are formed; see figs. 2H and 4); and a vertical connection structure (M2, V1-V3) is formed within a vertical connection region (regions between the resistive memory structures regions; see figs. 2H and 4) that is laterally offset from the memory array region in a plan view (see fig. 4).
Regarding Claim 19, Cheng discloses wherein: the lower-level metal interconnect structures (CP, M1, V1) comprise a column of first source contact via structures CP and a column of second source contact via structures CP (page 2, paragraph 17; see fig. 2B); one of the two first source lines SL is formed on the column of first source contact via structures CP (see fig. 2B); another of the two first source lines SL is formed on the column of second source contact via structures CP (see fig. 2B); and each source region S within the column of access transistors T is contacted by a respective one of the first source contact via structures CP and by a respective one of the second source contact via structures CP (see figs. 2B and 4).
Regarding Claim 20, Cheng discloses wherein: the upper-level metal interconnect structures (M2, V2, M3) comprises a bit line BL (page 4, paragraph 27) that overlies a horizontal plane including top surfaces of the column of resistive memory structures MU (see figs. 2I and 4) and electrically connected to top electrodes TE (page 3, paragraph 25) of the column of resistive memory structures MU (see figs. 2H and 4); and the second source line M3 is formed the bit line BL (see fig. 4).
Allowable Subject Matter
Claims 7-9 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 recites the plurality of interconnection via structures of the vertical connection structure comprises two first interconnection via structures each contacting a top surface of a respective one of the two first source lines and laterally spaced from each other along a second horizontal direction that is perpendicular to the first horizontal direction.
Claim 15 recites the metal interconnect structures comprise: two second source lines located at a second metal line level that is vertically spaced from the top surface of the semiconductor substrate by a second vertical spacing that is different from the first vertical spacing and laterally extending along the first horizontal direction; a first vertical connection structure providing a first electrical connection between one of the two first source lines and one of the two second source lines; and a second vertical connection structure providing a second electrical connection between another of two first source lines and another of the two second source lines.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claims 8 and 9 depend from claim 7, so they are objected for the same reason.
Conclusion
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 August 18, 2026
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