CTNF 18/629,474 CTNF 101644 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statements (IDS) submitted on 4/8/2024 and 3/3/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Drawings 06-36 AIA The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations “the backside bit line is wider than the frontside bit line.” (claim 8) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-02 AIA Claim 8 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The undescribed subject matter is “the backside bit line is wider than the frontside bit line” as it does not appear in the figures. The examiner notes that “It is the specification, not the knowledge of one skilled in the art, that must supply the novel aspects of an invention in order to constitute adequate enablement.” Genentech, Inc. v. Novo Nordisk A/S , 108 F.3d 1361, 1366 (Fed. Cir.1997). “Although the knowledge of one skilled in the art is indeed relevant, the novel aspect of an invention must be enabled in the patent.” Automotive Tech. V. BMW OF N. Am. , 501 F.3d 1274, 1283 (Fed. Cir. 2007) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-3 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayan (WO 2023183120 A1) in view of Wang (US 20190273084 A1) in further view of Bohr (US 11410928 B2) . Regarding claim 1, Naranyan teaches, in FIG. 20, a semiconductor device with a ‘Bitline Logic Circuit’ 2014 (with at least one logic cell), and a ‘Memory Array Bank’ (any one of 2012A-C) arranged in a row. FIG. 21 shows “Memory Array” 2100 which comprises a first ‘bank’ (first plurality of bit line cells) 2130B a second ‘bank’ (second plurality of bit line cells) 2130A arranged in a row as well as a frontside bit line 2120B and a backside bit line 2120A (the examiner notes that, although 2120B is depicted as being on a backside in FIG. 21, a Z-direction reversed perspective is equally valid in the present case). These bit lines make up frontside and backside interconnect structures. The backside bit line 2120A is coupled to the first plurality of the memory cells (see paragraph 00116) and the frontside bit line is coupled to both the first and second plurality of the memory cells in the row (see paragraph 0044). The examiner notes that the ‘Bitline Logic Circuit’ of FIG. 20 would correspond to the origin point of the bit lines 2120A and 2120B in FIG. 21, meaning that the first plurality of logic cells are positioned closed to the logic cell than the second plurality of logic cells. Naranyan does not explicitly teach that the frontside and backside bit lines are coupled. Wang teaches, in ‘Abstract,’ a ‘memory device’ (semiconductor device) comprising “a first plurality of memory cells, a second plurality of memory cells,” “a local bit line on a second level” and “a global bit line on a third level . . .” . Paragraph 0030 states: “the short local bit line uses interconnects on the backside of a semiconductor wafer, while the long global bit line uses interconnects on a frontside of the semiconductor wafer.” Furthermore, these bit lines are coupled via “sense amplifiers” (abstract). Wang does not teach that the bit lines are coupled via a source/drain feature in one of the first plurality of the memory cells. Bohr teaches a method for connecting frontside and backside metallization layers in which “one or more device layer interconnects that extend through the device layer of the 3D IC to provide a conductive connection between one or more of the frontside interconnects and one or more of the backside interconnects. The individual device layer interconnects may be formed in a diffusion region (e.g., source or drain region) or gate region of a dummy transistor (e.g., dummy FinFET) of the transistor array” (paragraph 30). Also see paragraph 29. It would have been obvious to modify the semiconductor device taught by Naranyan such that the front and backside bit lines are coupled, as taught by Wang, and that they are coupled by the source/drain feature of a pass-gate transistor, as taught by Bohr. The examiner notes that the first and second bit lines only vertically overlap in the region containing the first plurality of memory cells as taught by Naranyan (see FIG. 21), so the coupling taught by Wang and Bohr can only occur via the pass-gate transistor of one of the first plurality of memory cells. One having ordinary skill in the art is motivated to couple the transistors in order to implement a longer and shorter bit line: “The short local bit line may be optimized for low capacitance to reduce noise disturbance on a storage node of a memory cell during read operations. The long global bit line is optimized for low resistance to reduce delay of read and write operations” (Wang, paragraph 0031), and is motivated to couple them via a source/drain feature of one of the memory cells because it will “. . . enable a high-density and low-capacitance connection for signal routing between the frontside and backside of the 3D IC” (Bohr, paragraph 31). Regarding claim 2, Naranyan teaches, in FIG. 21, that the backside bit line 2120A does not extend to, and therefore is free of coupling to, the second plurality of the memory cells. Regarding claim 3, Naranyan teaches, in FIG. 21, that the second plurality of memory cells has less (3) memory rows than the first plurality of memory cells (5), and therefore it has less memory cells. Regarding claim 10, Naranyan further teaches in FIG. 11, a semiconductor device with a “Topside Via” 907C (which are source/drain contacts, see FIGs. 12-14 with source/drain feature) which fully overlaps with a “frontside metal layers portion” 908C and partially overlaps with “Backside Metal Layers Portion” 912A (which can correspond to frontside and backside bit lines). It would have been obvious to one having ordinary skill in the art to modify the frontside and backside bit lines taught by Naranyan such that the front side bit line completely overlaps a source/drain contact over a source/drain feature and so that the second bit line partially overlaps a source/drain contact below the source/drain feature. One having ordinary skill in the art is motivated to do so in order to, for example, offset the front and backside bit lines to minimize parasitic capacitance . 07-21-aia AIA Claim (s) 4-8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayan (WO 2023183120 A1) in view of Wang (US 20190273084 A1) in further view of Bohr (US 11410928 B2) and Park (TW I792943 B) . Regarding claim 4, as explained above, Naranyan, Wang, and Bohr teach the limitations of claim 1. Naranyan further teaches: “The present disclosure recognizes that redundant power connections can be made above and below the device to reduce the interface resistances in a standard cell layout” (paragraph 0041). Naranyan does not teach a backside bit line with nonuniform width. Park teaches, in paragraph two of ‘DISCLOSURE,’ a bit line “ . . . wherein the maximum width of the first portion of the bit line is greater than the maximum width of the second portion of the bit line.” It would have been obvious to one of ordinary skill in the art to further modify the device taught by Naranyan, Wang, and Bohr such that the backside bit line has a first portion coupled to the first plurality of memory cells and the second portion which is wider than the first portion which is coupled to the second plurality of memory cells. One having ordinary skill in the art is motivated to extend the backside bit line to couple to the second plurality of memory cells to provide the redundant connection benefit taught by Naranyan above, and to widen this second portion of the bit line in order to reduce the resistance of the line to garner the following benefit: “ Low local bit line resistance . . . reduces bit line signal development time and helps minimize disturbances on a storage node during a read operation.” (Wang, paragraph 0042). Regarding claim 5, as stated above, Naranyan teaches that a number of the second plurality of memory cells is less than a number of the first plurality of memory cells. Regarding claim 6, Wang further teaches, in paragraph 0060, an example in which “. . . the local bit line is wider than the global bit line.” It would have been obvious to one of ordinary skill in the art to further modify the device taught by Naranyan, Wang, and Bohr such that the frontside and backside bit lines are of a different width, as taught by Wang. One having ordinary skill in the art is motivated to do so in order to, for example, ensure that proper voltages are being delivered to memory cells by controlling the resistance of the wires via their widths as needed. Regarding claims 7 and 8, as explained above, Wang teaches in paragraph 0060 that a ‘local bit line’ (which is a frontside bit line, see above) is wider than a backside bit line. It would have been obvious to one of ordinary skill in the art to further modify the device taught by Naranyan, Wang, and Bohr such that the frontside bit line is wider than the backside bit line as taught by Wang. One having ordinary skill in the art is motivated to widen the frontside interconnect taught by Naranyan relative to the backside interconnect because it delivers voltage across a farther distance (all of the cells in the row), thus needing to be wider to ensure resistance is not too high: “Low local bit line resistance . . . reduces bit line signal development time and helps minimize disturbances on a storage node during a read operation.” (Wang, paragraph 0042). Additionally, it would have been obvious to one having ordinary skill in the art to further modify the device taught by Naranyan, Wang, and Bohr such that the backside bit line is wider than the frontside bit line as taught by Wang; the examiner notes that while Wang teaches a frontside bit line being wider than a backside bit line, 'frontside' and 'backside' directions are arbitrary and can be reversed. One having ordinary skill in the art is motivated to do so in order to, for example, minimize resistance in the backside bit line while minimizing the profile of the frontside bit line, minimizing parasitic capacitance. Regarding claim 9, as explained above, Naranyan, Wang, and Bohr teach the limitations of claim 1. Wang teaches that a backside bit line has a wider width than a frontside bitline. However, Naranyan, Wang, and Bohr teach both frontside and backside bit lines with uniform width. As explained above, Park teaches a bit line with a second portion that is wider than a first portion. It would have been obvious to one of ordinary skill in the art to further modify the device taught by Naranyan, Wang, and Bohr such that the backside bit line has a nonuniform width (specifically, a second portion that is wider than a first portion). One having ordinary skill in the art is motivated to do so in order to garner the benefits of reducing the resistance of the backside bit line - as taught by Wang above – for the second (farther) plurality of bit line cels, while also conserving space on the backside of the semiconductor device in the first portion (by keeping that portion thinner), were the resistance experienced by a signal to the nearer (first plurality) of cells is lesser due to a shorter current path . 07-21-aia AIA Claim (s) 11 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayan (WO 2023183120 A1) . Regarding claim 11, Naranyan teaches, in FIG. 20, a semiconductor device with a ‘Bitline Logic Circuit’ 2014 (with at least one logic cell), and a ‘Memory Array Bank’ (any one of 2012A-C) arranged in a row. FIG. 21 shows “Memory Array” 2100 which comprises a first ‘bank’ (first plurality of bit line cells) 2130B a second ‘bank’ (second plurality of bit line cells) 2130A arranged in a row as well as a frontside bit line 2120A and a backside bit line 2120B These bit lines make up frontside and backside interconnect structures disposed over and under the memory cells, respectively. The backside bit line 2120B is coupled to at least some of the memory cells in the row (see paragraph 0041). The frontside and backside bit lines partially overlap vertically (as the backside bit line is under the frontside bit line) and are both suggested to be coupled to the memory cells (see paragraph 0041). The examiner notes that the ‘Bitline Logic Circuit’ of FIG. 20 would correspond to the origin point of the bit lines 2120A and 2120B in FIG. 21, meaning that the first plurality of logic cells are positioned closer to the logic cell than the second plurality of logic cells. It would have been obvious to modify the semiconductor device taught by Naranyan such that both the frontside and backside bit lines are coupled to the memory cells. One having ordinary skill in the art is motivated to do so because of the following benefit taught by Naranyan “The present disclosure recognizes that redundant power connections can be made above and below the device to reduce the interface resistances in a standard cell layout” (paragraph 0041). Regarding claim 15, in a separate interpretation of that of claim 11, the (previously interpreted) frontside bit line 2120 A of FIG. 21 can be interpreted to be the backside bit line, and the (previously interpreted) backside bit line 2120B can be interpreted to be the frontside bit line (as the Z direction is arbitrary, see above). The frontside bit line 2120B is coupled to each of the memory cells in the row (see above) and the backside bit line is free of coupling to at least one of the memory cells arranged in a row (the second plurality of memory cells). Regarding claim 16, Naranyan further teaches, in FIG. 21, that the backside bit line is coupled to each of the memory cells arranged in the row (see above), and the frontside bit line is free of coupling to at least one of the memory cells arranged in the row (the second plurality of memory cells) . 07-21-aia AIA Claim (s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayan (WO 2023183120 A1) in view of Wang (US 20190273084 A1) . Regarding claim 12, as explained above, Naranyan teaches the limitations of claim 11. Naranyan does not teach that the backside bit line is thicker than the frontside bit line. Wang teaches , in paragraph 0060, an example in which “. . . the local bit line is wider than the global bit line.” The examiner notes that while the local bit line is a frontside bit line and the global bit line is a backside bit line, the Z direction is arbitrary and can be flipped. The examiner notes that while the word ‘wider’ is used here, this is synonymous with the word thicker as it is used in the art . It would have been obvious to one of ordinary skill in the art to modify the device taught by Naranyan such that the backside bit line is thicker than the frontside bit line. One having ordinary skill in the art is motivated to do so in order to, for example, reduce the resistance to the memory cells. Regarding claim 13, as explained above, Naranyan teaches the limitations of claim 11. Naranyan does not teach that the frontside bit line is wider than the backside bit line. Wang teaches, in paragraph 0060, an example in which “. . . the local bit line is wider than the global bit line.” The examiner notes that the local bit line is on the front side and the global bit line is on the backside (see above). It would have been obvious to one of ordinary skill in the art to further modify the device taught by Naranyan such that the frontside bit line is thicker than the backside bit line, as taught by Wang. One having ordinary skill in the art is motivated to do so in order to garner the benefits of minimizing local bit line resistance taught by Wang above . 07-21-aia AIA Claim (s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayan (WO 2023183120 A1) in view of Yang (US 20210098049 A1) Regarding claim 14, Naranyan further teaches, in FIG. 21 (this time referring to memory array 2150) a second backside bit line 2170C which couples to a second plurality of cells (2180B in the 2150 memory array). Naranyan does not teach that the first backside bit line is wider than the second backside bit line in a cross sectional view. Yang teaches, in ‘BACKGROUND,” the following relationship between bit line dimensions and memory cell operability: “As the bit line dimensions shrink, the voltage drop (also known as ohmic drop or IR drop) due to bit line resistance may lower the supply voltage to distant SRAM cells to a level below the threshold voltage to operate these distant SRAM cells, resulting in inoperative SRAM cells or failed bits.” It would have been obvious to one of ordinary skill in the art to modify the semiconductor device taught by Naranyan such that the backside interconnect comprises a second bit line in which the first bit line is wider than the second bit line in in a cross-sectional view. One having ordinary skill in the art is motivated to do so to ensure that the cells coupled to the second bit line do not fail, as taught by Yang . 07-21-aia AIA Claim (s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayan (WO 2023183120 A1) in view of Wang (US 20190273084 A1) in further view of Bohr (US 11410928 B2) and Tran (US 20050040450 A1) . Regarding claim 17, as explained above, Naranyan teaches the limitations of claim 11. Narayan also teaches that the frontside bit line has a uniform width (as is inherent of a bit line in which it is not disclosed that a nonuniform width is present). Tran teaches, in FIG. 2, a series of bit lines 32 that have main portions (see center of figure) with jogs protruding from the main portion. It would have been obvious to one of ordinary skill in the art to modify the semiconductor device taught by Naranyan such that the backside bit lines has a main portion and jogs One having ordinary skill in the art is motivated to do so because the jogs allow for the advantageous routing of bit lines to aid in “ . . . achieving the desired memory cell area reduction” (Tran, paragraph 0033) . 07-21-aia AIA Claim (s) 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayan (WO 2023183120 A1) in view of Park (TW I792943 B) . Regarding claim 18, Naranyan teaches, in FIG. 20, a semiconductor device with a ‘Bitline Logic Circuit’ 2014 (with at least one logic cell), adjacent to a ‘Memory Array Bank’ (any one of 2012A-C) arranged in a row. FIG. 21 shows “Memory Array” 2160 which has M rows and N columns, as well as a frontside bit line (frontside signal line) 2170A disposed directly above one of the M rows and a backside bit line (backside signal line) 2170B disposed directly under one of the M rows. These bit lines make up frontside and backside interconnect structures. Though first bit line 2120A is coupled to the first plurality of the memory cells (see paragraph 00116, paragraph 0041 states: “The present disclosure recognizes that redundant power connections can be made above and below the device to reduce the interface resistances in a standard cell layout.” The backside bit line 2170B has a first portion that connects from a 1st to a (Q-1)th column and second portion that connects from a Qth column to an Nth column. The examiner notes that the ‘Bitline Logic Circuit’ of FIG. 20 would correspond to the origin point of the bit lines 2120A and 2120B in FIG. 21, meaning that the first column is closer to the logic region than the Nth column. PNG media_image1.png 705 585 media_image1.png Greyscale Naranyan does not teach that the second segment of the backside bit line has a smaller width than a first width of the first segment. As explained above, park teaches a bit line that has a second portion that is wider than a first portion. It would have been obvious to one having ordinary skill in the art to modify the semiconductor device taught by Naranyan such that the backside bit line has a first portion which connects from a 1st to a (Q-1)th column and a second portion which is wider and connects from a Qth to an Nth column. One having ordinary skill in the art is motivated to do so because the Qth to Nth columns have a distance that a current must travel to a memory cell that is greater than a first portion, thus the wider bit line in the second portion ensures that the resistance in the wire is not too high as to render the device inoperable. Regarding claim 20, Naranyan further teaches, in FIG. 21, that N is 8 and Q is 7, so N-Q+1 is 2, which is ¼ of N . 07-21-aia AIA Claim (s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayan (WO 2023183120 A1) in view of Park (TW I792943 B) and Wei (US 20230083548 A1) in further view of Yang (US 20210098049 A1) . Regarding claim 19, as explained above, Naranyan and Park each the limitations of claim 18. Naranyan and park do not each that N is larger than 128 and N-Q+1 is not larger than 64. Wei teaches, in paragraph 0015 a “memory Array” which “ . . . includes memory cells 112 arranged in columns and rows (not labeled)” in which “memory array 110 includes the number of rows ranging from 128 to 512.” That is, Wei teaches that N is greater than 128. Wei does not teach a backside bit line which has a first segment extending from a first to a (Q-1)th memory cell and a segment that extends from a (Q-1)th to an Nth memory cell and that N-Q+1 is not larger than 64. Yang teaches, in ‘BACKGROUND,” the following relationship between bit line dimensions and memory cell operability: “As the bit line dimensions shrink, the voltage drop (also known as ohmic drop or IR drop) due to bit line resistance may lower the supply voltage to distant SRAM cells to a level below the threshold voltage to operate these distant SRAM cells, resulting in inoperative SRAM cells or failed bits.” The examiner notes that Q determines the number of memory cells the first segment of the backside bit line spans before it grows wider (thus reducing the resistance of the bit line per unit length). Thus, it would have been obvious to one of the ordinary skill in the art to modify the semiconductor device taught by Naranyan and Park such that the device has an N that is greater than 128 (in order to, for example, increase device storage without having too many rows as to render the device inoperable by having too long of a bit line, as taught by Yang) and such that the device has a Q wherein N-Q+1 is not larger than 64 with routine experiment and optimization since this determines the operability of the device (as distant memory cells need to be kept under a bit line resistance threshold to ensure operability, as taught by Yang). See In re Woodruff , 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch , 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller , 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /G.S.M./ Examiner, Art Unit 2897 /JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897 Application/Control Number: 18/629,474 Page 2 Art Unit: 2897 Application/Control Number: 18/629,474 Page 3 Art Unit: 2897 Application/Control Number: 18/629,474 Page 4 Art Unit: 2897 Application/Control Number: 18/629,474 Page 5 Art Unit: 2897 Application/Control Number: 18/629,474 Page 6 Art Unit: 2897 Application/Control Number: 18/629,474 Page 7 Art Unit: 2897 Application/Control Number: 18/629,474 Page 8 Art Unit: 2897 Application/Control Number: 18/629,474 Page 9 Art Unit: 2897 Application/Control Number: 18/629,474 Page 10 Art Unit: 2897 Application/Control Number: 18/629,474 Page 11 Art Unit: 2897 Application/Control Number: 18/629,474 Page 12 Art Unit: 2897 Application/Control Number: 18/629,474 Page 13 Art Unit: 2897 Application/Control Number: 18/629,474 Page 14 Art Unit: 2897
Prosecution Insights