DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-17, 21-23 and 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0010770 A1 to Joo et al. (hereinafter “Joo”).
Regarding claim 1, Joo discloses a device package configured with a lead alignment construction (semiconductor device 10 having construction for aligning leads; Figs. 6A-7; paragraphs [0059]-[0062]), the device package comprising:
a plurality of leads comprising lead structures configured as part of a leadframe during manufacturing (leads 30a-30e each having a structure capable of being a part of a leadframe during manufacturing; Figs. 6A-7; paragraphs [0059]-[0062]);
the plurality of leads further comprising attachment pads (plurality of leads 30a-30e each having portion of conductive layer 55 which may be a pad to attach the leads 30a-30e to board 50; Figs. 6A-7; paragraphs [0037], [0059]-[0062]); and
a lead alignment construction comprising one or more of the attachment pads being implemented with a solder mask material configured to promote alignment of all of the plurality of leads attached to the leadframe during solder reflow (the construction of device 10 is such that leads 30a-30e are aligned on pad portions of layer 55 via epoxy 70 and solder dam 90, with solder 75 used to bond the leads 30a-30e to the layer 55 and capable of promoting alignment of the leads 30a-30e of leadframe during a solder reflow; Figs. 6A-7; paragraphs [0059]-[0062]).
Regarding claim 2, Joo discloses the device package according to claim 1 wherein the solder mask material at least partially surrounds an exposed metal area of one or more of the attachment pads adjacent an attachment end of the plurality of leads (epoxy 70 and solder dam 90 at least partially surrounds exposed metal area of pad portions of conductive layer 55 adjacent attachment end of leads 30a-30e; Figs. 6A-7).
Regarding claim 3, Joo discloses the device package according to claim 1 wherein the solder mask material is configured with dimensions to promote an alignment of the plurality of leads to one or more of the attachment pads during solder reflow (epoxy 70 and solder dam 90 have dimensions capable of promoting alignment of leads 30a-30e to pad portions of layer 55 during reflow; abstract; Figs. 6A-7).
Regarding claim 4, Joo discloses the device package according to claim 1 wherein one or more of the attachment pads are configured with dimensions to promote an alignment of the plurality of leads during solder reflow (pad portions of layer 55 have dimensions capable of promoting alignment of leads 30a-30e during reflow; abstract; Figs. 6A-7).
Regarding claim 5, Joo discloses the device package according to claim 1 wherein the solder mask material is arranged along at least two sides of one or more of the attachment pads (epoxy 70 and solder dam 90 arranged along at least two sides of pad portions of layer 55; Figs. 6A-7).
Regarding claim 7, Joo discloses the device package according to claim 1 wherein the solder mask material is arranged such that there is an attachment area configured to receive solder for attachment of the plurality of leads to one or more of the attachment pads (epoxy 70 and solder dam 90 arranged such that there exists a space capable of receiving solder 75 for attachment of leads 30a-30e to pad portions of layer 55; Figs. 6A-7).
Regarding claim 8, Joo discloses the device package according to claim 7 wherein an arrangement of the solder mask material forms the attachment area on one or more of the attachment pads without any of the solder mask material arranged thereon (epoxy 70 and solder dam 90 arranged such that there exists a space on pad portions of layer 55 without any of the epoxy 70 and solder dam 90 thereon; Figs. 6A-7).
Regarding claim 9, Joo discloses the device package according to claim 1 wherein one or more of the attachment pads comprise a first pad side, a second pad side, a third pad side, and a fourth pad side, which is arranged adjacent a device side; and wherein the solder mask material is arranged to extend from the second pad side to the first pad side adjacent the third pad side (pad portions of layer 55 comprise at least four sides and arranged adjacent a side of device 10, where epoxy 70 and solder dam 90 arranged to extend from second to first side of pads adjacent third side; Figs. 6A-7).
Regarding claim 10, Joo discloses the device package according to claim 9 wherein the solder mask material is further arranged to extend from the fourth pad side to the second pad side of one or more of the attachment pads adjacent the first pad side (epoxy 70 and solder dam 90 arranged to extend from fourth to second side of pads adjacent first side; Figs. 6A-7).
Regarding claim 11, Joo discloses the device package according to claim 9 wherein the solder mask material is further arranged to extend from the first pad side to the third pad side adjacent the second pad side (epoxy 70 and solder dam 90 arranged to extend from first to third side of pads adjacent second side; Figs. 6A-7).
Regarding claim 12, Joo discloses the device package according to claim 9 wherein the solder mask material is further arranged to extend from the fourth pad side to the second pad side of one or more of the attachment pads adjacent the first pad side (epoxy 70 and solder dam 90 arranged to extend from fourth to second side of pads adjacent first side; Figs. 6A-7); and wherein the solder mask material is further arranged to extend from the first pad side to the third pad side adjacent the second pad side (epoxy 70 and solder dam 90 arranged to extend from first to third side of pads adjacent second side; Figs. 6A-7).
Regarding claim 13, Joo discloses the device package according to claim 9 wherein an attachment area comprises an attach width comprising a distance between the second pad side and the fourth pad side without the solder mask material; and wherein the attach width is 10 % – 80 % greater than a lead width (distance between second and fourth side of pads is roughly 50% greater than lead 30a-30e width; Figs. 6A-7).
Regarding claim 14, Joo discloses the device package according to claim 1 wherein one of the attachment pads is implemented without the solder mask material (epoxy 70 and solder dam 90 may be partially arranged in a ring around board 50 such that it is not applied to all pads of layer 55; paragraph [0038]).
Regarding claim 15, Joo discloses the device package according to claim 1 wherein some of the plurality of leads are arranged on a device side; and wherein two inner implementations of the plurality of leads on the device side are implemented with the lead alignment construction (leads 30a-30e arranged on side of device 10, where two inner leads are implemented in manner to be aligned on pad portions of layer 55 via epoxy 70 and solder dam 90; Figs. 6A-7; paragraphs [0059]-[0062]).
Regarding claim 16, Joo discloses the device package according to claim 15 wherein at least one of the plurality of leads on the device side are implemented without the lead alignment construction (each of leads 30a-30e may be implemented in a non-uniform manner with epoxy 70 formed in ring around board 50; Fig. 7; paragraph [0038]).
Regarding claim 17, Joo discloses the device package according to claim 15 wherein a center one of the plurality of leads on the device side is implemented without the lead alignment construction (central lead 30c may not have epoxy 70 disposed thereover when utilized in ring around board 50; Fig. 7; paragraph [0038]).
Regarding claim 21, Joo discloses the device package according to claim 1 wherein at least one of the lead structures is narrower than another one of the lead structures (lead 30c narrower than other leads 30; Fig. 7).
Regarding claim 22, Joo discloses the device package according to claim 1 comprising a RF package, a RF amplifier package, a RF power amplifier package, a RF power transistor package, and/or a RF power amplifier transistor package (layer 55 of device 10 may comprise RF circuitry supporting radio communication over UHF or higher frequency bands; paragraph [0058]).
Regarding claim 23, Joo discloses the device package according to claim 1 comprising one or more semiconductor devices and a support, wherein the one or more semiconductor devices are attached to the support (semiconductor devices 10, 20 having supporting submount 60 and mount areas; paragraphs [0037] and [0039]-[0041]).
Regarding claim 28, Joo discloses a process of implementing a device package with a lead alignment construction (semiconductor device 10 having construction for aligning leads; Figs. 6A-7; paragraphs [0059]-[0062]), the process comprising:
configuring a plurality of leads comprising lead structures as part of a leadframe during manufacturing (leads 30a-30e each having a structure capable of being a part of a leadframe during manufacturing; Figs. 6A-7; paragraphs [0059]-[0062]);
configuring the plurality of leads with attachment pads (plurality of leads 30a-30e each having portion of conductive layer 55 which may be a pad to attach the leads 30a-30e to board 50; Figs. 6A-7; paragraphs [0037], [0059]-[0062]); and
configuring a lead alignment construction comprising one or more of the attachment pads being implemented with a solder mask material configured to promote alignment of all of the plurality of leads attached to the leadframe during solder reflow (the construction of device 10 is such that leads 30a-30e are aligned on pad portions of layer 55 via epoxy 70 and solder dam 90, with solder 75 used to bond the leads 30a-30e to the layer 55 and capable of promoting alignment of the leads 30a-30e of leadframe during a solder reflow; Figs. 6A-7; paragraphs [0059]-[0062]).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2016/0329269 A1 to Shih, US 2023/0238313 A1 to Xiaorui et al., and US 2023/0395465 A1 to Ho et al. each discloses semiconductor package structures having related lead, pad, and solder mask arrangements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818