Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The examiner notes that non-English language foreign patent documents are relied upon in this action. Hereafter, all quotes, paragraph numbers, and figure numbers of foreign patent documents refer to the translations thereof attached to this action.
Claim(s) 1-6, 8-9, 16-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20100065849 A1) in view of Lin (TW 202212943 A).
Regarding claim 1, Lee teaches, in FIG. 1, a display panel comprising display region ‘P’ with ‘gate lines’ (scan lines) 32 and ‘data lines’ 34, which are disposed on substrate 12. Paragraph 001 states: “The gate lines and data lines cross each other to define the pixels” (plurality of pixel structures). FIG. 2 shows a pixel structure, coupled to a transistor T2 (display transistor) with semiconductor ‘layer’ (pattern) 42, source electrode 52, drain electrode 56, and gate electrode 38 in which (“. . . the thin film transistors T1 and T2 [are] connected to the gate line 32 and the data line 34 . . .” (the gate is connected to the scan line, paragraph 0073). The source electrode 52 is “branched from the data line 34” (data line is connected to source electrode, paragraph 0079). Fig. 2 further shoes ‘first electrode’ 16 connected to organic light emitting layer 18 and drain electrode 56 (pixel electrode), and ‘light blocking layer’ 60 disposed between the first gate electrode and the substrate, and having a first opening overlapping the first gate electrode.
Lee does not teach that the first gate electrode is disposed between the substrate and the first semiconductor pattern.
Lin teaches, in FIG. 6B, a display panel with a gate electrode 114, which is located between a substrate 100 and semiconductor channel 130. It would have been obvious to one of ordinary skill in the art to modify the display panel taught by Lee such that the gate is disposed between the substrate and the semiconductor layer, as taught by Lin. One having ordinary skill in the art is motivated to do so in order to, for example, decrease parasitic capacitance by distancing the gate electrode from other conductive elements.
Regarding claim 2, Lee further teaches in FIG. 2, that the light shielding pattern on the substrate is located within an orthogonal projection of the first gate electrode on the substrate.
Regarding claim 3, Lee further teaches, in FIG. 2, an orthogonal projection of the light shielding pattern layer on the substrate surrounds an orthogonal projection of the first gate electrode on the substrate.
Regarding claim 4, Lin further teaches, in FIG. 4B, a ‘branch portion’ of 116B of a common electrode (see paragraph 26 of Mode-for-Invention) which is located between substrate 100 and pixel electrode 190 and which forms a gap between it and the gate electrode 114 which is located within the orthogonal projection of ‘light shielding electrode’ (light shielding layer) 170 on the substrate.
It would have been obvious to one having ordinary skill in the art to modify the device taught by Lee such that the device comprises a common electrode disposed between the pixel electrode and the substrate, and overlapping the pixel electrode and which forms a gap between it and the gate electrode, with the gap being located in an orthogonal projection of the light shielding layer. One having ordinary skill in the art is motivated to construct a common electrode in order to provide a shared electrical contact between pixels and to form the aforementioned gap and light shielding orientation in order to, for example, to prevent light from the emission region from entering the gap between these components, preventing damage to photosensitive films.
Regarding claim 5, Lin further teaches, in FIG. 2A, an orthogonal projection of the common electrode 116 and an adjacent ‘data line’ 142 which have a second gap (see dotted line on annotated figure) located within an orthogonal projection of the light shielding layer 170 on the substrate.
PNG
media_image1.png
822
883
media_image1.png
Greyscale
It would have been obvious to one having ordinary skill in the art to further modify the device taught by Lee such that a second gap between the common electrode and an adjacent data line is located in an orthogonal projection of the light shielding pattern layer, as taught by Lin. One having ordinary skill in the art is motivated to do so in order to, for example, ensure that light cannot enter the gap and damage photosensitive components.
Regarding claim 6, Lin further teaches, in FIG. 2A, an orthogonal projection of the common electrode 116 and an adjacent ‘scan line’ 112 which has a third gap (see above annotated figure) which is located in an orthogonal projection of the light shielding pattern layer on the substrate.
It would have been obvious to one having ordinary skill in the art to further modify the device taught by Lee such that orthogonal projections of the common electrode and adjacent scan line have a third gap which is located within the orthogonal projection of the light shielding pattern layer, as taught by Lin. One having ordinary skill in the art is motivated to do so in order to, for example, ensure that light does not enter the gap and damage photosensitive components.
Regarding claim 8, Lin further teaches, in FIG. 2A, that the orthogonal projection of the light shielding pattern layer on the substrate surrounds an orthogonal projection of the common electrode on the substrate.
It would have been obvious to one having ordinary skill in the art to further modify the device taught by Lee such that the orthogonal projection of the light shielding pattern layer on the substrate surrounds an orthogonal projection of the common electrode on the substrate, as taught by Lin. One having ordinary skill in the art is motivated to do so in order to, for example, ensure that the photosensitive components surrounding the common electrode are protected from light.
Regarding claim 9, Lee further teaches, in FIG. 2, that the light shielding layer is not electrically coupled to another element (and therefore has a floating potential).
Regarding claim 16, as shown above, Lee teaches first openings in a light shielding layer overlapping first gate electrodes. Lee further teaches, in paragraph 0058: ". . . according to an embodiment of the present invention, when the light blocking layer 60 is divided into a plurality of parts, charges are less accumulated as compared with the prior division of the light blocking layer 60, so that electro-static discharge can be reduced.”
It would have been obvious to one having ordinary skill in the art to modify the light shielding layer taught by Lee such that it is divided into a plurality of light shielding layers, for the reasons taught by Lee above.
Regarding claim 17, Lin further teaches, in FIG. 2B, that the pixel structures comprise a common electrode 116 which is disposed on the substrate, overlapping the pixel electrode, and which has an opening overlapping the first semiconductor pattern 130 (see the dotted line on the annotated FIG. 2A below).
PNG
media_image2.png
534
621
media_image2.png
Greyscale
It would have been obvious to one having ordinary skill in the art to further modify the display panel taught by Lee such that it comprises a common electrode which overlaps the pixel electrode and has an opening overlapping the first semiconductor pattern, as taught by Lin. One having ordinary skill in the art is motivated to form a common electrode in order to, for example, form a common voltage between adjacent pixels, and to form it overlapping with the pixel electrode as to enable an electrical field production therebetween, without influencing other components, and to form the opening overlapping the first semiconductor pattern in order to
Regarding claim 20, Lee further teaches, “the light blocking layer 60 is formed by using metal oxide and metal having a low reflectivity” (paragraph 0045).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20100065849 A1) in view of Lin (TW 202212943 A) in further view of Hosoya (JP 7018918 B2).
The examiner notes that the inventor name “Hosoya” is a romanization of an inventor name as it appears in the attached patent document.
Regarding claim 7, as explained above, Lee and Lin teach the limitations of claim 4. As explained above, Lin teaches a common electrode. They do not teach a reflective pattern.
Hosoya teaches, in FIG. 24B, a ‘reflective electrode’ 502 which is electrically connected to ‘pixel electrode’ (reflective layer) 106, which defines a reflective area of the pixel structure, and the areas that are not covered by the reflective layer define a transmissive area. Hosoya further teaches, in paragraph 91 of Description of Embodiments, “Further, according to the present embodiment, the electrode connected to the pixel electrode and formed of the same material as the drain electrode and the same layer as described in the first method described in the ‘background technique’ is used as the capacitive electrode.” This describes an electrode “in the same layer as” the drain electrode 105 (see FIG. 24B) which is connected to the pixel electrode 106 (the contact region for which is entirely disposed in the reflective area; therefore, the capacitive electrode must also be disposed in the reflective area). The examiner notes that paragraph 91 of Description of Embodiments contemplates embodiments in which the capacitive electrode is part of the drain electrode, but this still constitutes a capacitive electrode by function.
It would have been obvious to further modify the display panel taught by Lee such that the device comprises a common electrode as taught by Lin, and such that it further comprises a reflective layer covering and electrically electrode, a reflective and transmission region defined by the reflective layer, and a capacitive electrode disposed in the reflective area and connected to the pixel electrode, as taught by Hosoya. One having ordinary skill in the art is motivated to add a reflective layer as with it “ it is possible to use external light and reduce power consumption” (Hosoya, paragraph 199 of Description of Embodiments), and to add a capacitive electrode and to dispose the capacitive electrode to overlap the common electrode to achieve the following benefit: “. . . each pixel is used to maintain the potential of the pixel electrode for a period after writing to an arbitrary line is completed until writing is performed in the next cycle. [The pixels are] provided with an auxiliary capacity (Cs)” (Hosoya, paragraph 23 of Background Art); further the capacitive electrode should be coupled to the pixel electrode to apply the potential to the light emitting element (see above), and should be disposed in the reflective area to prevent degradation of the electrode from light.
Claim(s) 10-12 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20100065849 A1) in view of Lin (TW 202212943 A) in further view of Wang (US 20230169906 A1).
Regarding claim 10, as explained above, Lee and Lin teach the limitations of claim 1. They do not explicitly teach gate driving and shift register circuits.
Wang teaches, in FIG. 1 a gate driving circuit in which “a gate driving circuit is disposed in the frame region 6, and includes a plurality of cascaded shift registers (GOAs, Gate on Array) 14, where the shift registers 14 are . . . [each] connected to one gate line 8” (paragraph 0065). The examiner notes that the ‘gate lines’ correspond are scan lines. Furthermore, FIG. 1 shows this gate driving circuit as being disposed in a peripheral region away from the display region. Further, paragraph 0066 states: “the shift register (GOA) is a gate driving circuit formed by a plurality of thin film transistors . . . having a common gate electrode . . . a common source electrode . . . and a common drain electrode.” FIG. 4 further shoes that the source and drain electrodes (109 and 108, respectively) are connected to different parts of the source area.
It would have been obvious to one of ordinary skill in the art to further modify the display panel taught by Lee such that it comprises a peripheral gate driving circuit with shift register circuits with transistors, as taught by Wang. One having ordinary skill in the art is motivated to form a gate driving circuit and shift register circuits taught by Wang in order to simplify the structure of the display device (Wang, paragraph 0002). Additionally, forming a second opening in the light shielding layer amounts to a duplication of parts of the structure taught by Lee in FIG. 2 (that is, the opening in the light shielding layer overlapping the first gate electrode, see above). Also see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 11, Lee teaches in FIG. 2, that the orthogonal projection of the first opening of the light shielding pattern layer on the substrate is located within an orthogonal projection of the first gate electrode on the substrate (see above).
It would have been obvious to further modify the display panel taught by Lee such that the gates of the transistors of the shift register circuits (taught by Wang) have an orthogonal projection on the substrate that overlaps with the second opening (see above) as this amounts to a duplications of parts of the structure taught by Lee in FIG. 2 (that is, the opening in the light shielding layer overlapping the first gate electrode, see above). Also see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 12, Lee teaches, in FIG. 2, that an orthogonal projection of the light shielding pattern layer on the substrate surrounds an orthogonal projection of the first gate electrode on the substrate.
It would have been obvious to further modify the display panel taught by Lee such that an orthogonal projection of the light shielding pattern layer on the substrate surrounds an orthogonal projection of the first gate electrode on the substrate (see above) as this amounts to a duplications of parts of the structure taught by Lee in FIG. 2 (that is, the opening in the light shielding layer overlapping the first gate electrode, see above). Also see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 15, Wang further teaches, in FIG. 2, a circuit diagram for each of the shift register circuits in which each of the shift register circuits comprises an output stage circuit (see annotated FIG. 2 below), the output stage circuit is configured with an output transistor of the transistors (M11), the second gate electrode of the output transistor is electrically connected to a pull-down circuit (the output thereof is denoted PD) and a pull-up circuit (the output thereof is denoted PU), the second drain electrode of the output transistor is electrically connected to one of the scan lines (denoted GOUT_, the second source electrode of the output transistor is electrically connected to a clock signal line (CLK), wherein the pull-down circuit and the pull-up circuit are respectively configured with a part of the transistors.
PNG
media_image3.png
765
1742
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art to further modify the display device taught by Lee such that it comprises the shift register circuit taught by Wang above. One having ordinary skill in the art is motivated to do so because the described circuit allows for the proper control of signals to the gates of pixel transistors.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20100065849 A1) in view of Lin (TW 202212943 A) in further view of Wang (US 20230169906 A1) and Zhou (CN 110346990 A).
Regarding claim 13, Wang further teaches, in FIG. 4, a signal line (see attached annotated image):
PNG
media_image4.png
481
1147
media_image4.png
Greyscale
Wang does not teach a glue pattern and Wang nor Lee explicitly teach the transmittance of components in a peripheral region.
Zhou teaches, in Abstract, a “GOA circuit and its display panel” (Gate Driver on Array, which is a gate driving shift register circuit), Background paragraph 1 states that this contains TFTs), and “a panel frame glue line arranged above the GOA circuit.” further in Background paragraph 1, that in order to achieve a “fully solidified frame glue,” UV light must reach the glue pattern. Background paragraph 5 states “a GOA circuit 20 in the prior art [ensures] the design mode of 50% transmittance, [bringing] the advantages of easy-solidified frame glue.”
It would have been obvious to one having ordinary skill in the art to further modify the display panel taught by Lee such that signal lines are included, as taught by Wang, and to include a glue pattern in the peripheral portion and ensure that the transmittance of the signal lines, shift register circuits, and the light shielding pattern is greater than 38%, as taught by Zhou. One having ordinary skill in the art is motivated to include the (solidified) glue pattern in order to avoid “puncturing pollution” (Zhou, Background paragraph 1), and is motivated to create a transmittance greater than 38% to ensure that UV light can permeate the peripheral portion and solidify the glue frame (Zhou, Background paragraph 1).
Regarding claim 14, as explained above, Wang teaches shift register circuits away from a display region and Zhou teaches a glue pattern on the shift register circuits (gate driving array). The examiner notes that the glue pattern will therefore inherently have an outer edge away from the display area.
They do not explicitly teach a distance between a signal line closest to an outer edge of the glue pattern and the outer edge of a glue pattern.
However, the specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon thicknesses or upon another variable recited in a claim, the Applicant must show that the thicknesses are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20100065849 A1) in view of Lin (TW 202212943 A) in further view of Xi (WO 2023178560 A1).
Regarding claim 17, as explained above, Lee and Lin teach the limitations of claim 1. They do not teach a common electrode, disposed on the substrate, overlapping the pixel electrode, and having an opening overlapping the first semiconductor pattern.
Xi teaches, in FIG. 5, a common electrode 106’, disposed on a substrate 101, overlapping a pixel electrode 105, and having an opening in ‘slits’ overlapping the first semiconductor pattern (unlabeled channel region of TFT).
It would have been obvious to one having ordinary skill in the art to further modify the device taught by Lee such that the pixel structures comprise a common electrode, disposed on the substrate, overlapping the pixel electrode, and having an opening overlapping the first semiconductor pattern, as taught by Xi. One having ordinary skill in the art is motivated to form a common electrode overlapping the pixel electrode in order to create an electric field between the two components, and to form an opening overlapping the first semiconductor pattern in order to, for example, enable light treatment of the semiconductor pattern (for example, laser-enabled melting to form polysilicon out of amorphous silicon).
Regarding claim 18, Xi further teaches, in FIG. 5, that the pixel electrode is located between the common electrode and the substrate, the common electrode is configured with a plurality of “slits” (see paragraph 38 of Detailed Ways, one having ordinary skill in the art appreciates this to be on a micro-scale, that is, that the slits are micro-slits), and the micro-slits overlap the pixel electrode.
It would have been obvious to further modify the device taught by Lee such that the pixel electrode is located between the common electrode and the substrate, the common electrode is configured with a plurality of micro-slits, and the micro-slits overlap the pixel electrode, as taught by Xi. One having ordinary skill in the art is motivated to form the pixel electrode between the common electrode in the substrate in order to, for example, improve the planarity of the common electrode, and to form micro-slits in the electrode in order to, for example, form bends in the electric field emitted from the common electrode, improving the display qualities of an LCD layer.
Regarding claim 19, Lin further teaches, in FIG. 4A, a common electrode 116A-B (branches of the common electrode, see above) that overlaps one of the data lines 142 and one of the scan lines 112.
It would have been obvious to one having ordinary skill in the art to further modify the display device taught by Lee such that the common electrode overlaps one of the data lines and one of the scan lines, as taught by Lee. One having ordinary skill in the art is motivated to do so in order save space in the device and reduce size.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kurasawa (US 20180129327 A1) – Device comprising an array display panel (see FIG. 2) and a light shielding layer 182 with a plurality of gaps disposed over a display device, gaps overlap transistors, electrodes, etc. (see FIG. 4).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/G.S.M./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights