DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Rejections under 35 USC 102 and 103
Applicant’s amendments filed 04/13/2026 with respect to Claim(s) 1-20 have been fully considered but they are not persuasive.
Applicant(s) have presented arguments/amended independent claim(s) 1, 14 and 18 to patentably distinguish over prior art of Eldridge alone or in combination with others, however the Examiner believes that Eldridge alone or in combination with others still teaches the amended limitations.
As to applicant(s) argument of [1] “all DUTs 34 are concurrently activated for testing in Eldridge rather than being activated one by one sequentially”, the Examiner respectfully disagrees. Eldridge teaches test sequence where DUTs can be tested either individually/separately or concurrently/collectively (see col. 11 lines 1-2 :- It should be apparent that probe card 50 may make connections with one DUT as shown in FIG. 18 or a plurality of DUTs, for example, as shown in FIG. 14; col. 16 lines 1-3 :- more than one main power supply provide power to DUTs; clm. 10 - determines the expected input demand based on a measurement of an actual power demand of a reference semiconductor for an individual cycle of the test sequence).
As to applicant(s) argument of [2] “Eldridge also fails to disclose that the main power supply 36 (e.g., alleged auxiliary control circuit) can provide the voltage VA/VB only to the second terminal (e.g., lower terminal) of each remaining switches SW2 deactivated by the IC tester 30 (e.g., alleged control circuit) while one switch SW1 is activated.”, the Examiner respectfully disagrees. Eldridge in Fig. 5 clearly illustrates if SW1 and/or SW2 is deactivated/off, second terminal of SW2 = one terminal of R2 = have a voltage of [Vb – (I3=0) * R2] = Vb which is interpreted as second power supply voltage from auxiliary control circuit.
Therefore, Examiner believes Eldridge teaches the claimed limitation(s).
Based on the arguments presented above, the Examiner strongly believes Eldridge alone or in combination with others meets the current limitations for Claim(s) 1-20.
For further details see the rejections/objections for Claim(s) 1-20 herein.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7-11, 14 and 17-18 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Eldridge et al. (US 7714603; hereinafter Eldridge).
Regarding claim 1, Eldridge discloses in figure(s) 1-26 a testing apparatus, comprising:
a plurality of devices under test (DUTs) (34; fig. 5); and
an advanced process control monitor (APCM) (30,32,36,38), comprising:
a switch circuit (32), comprising a plurality of switch devices (SW2) corresponding to the DUTs;
a control circuit (30), comprising a plurality of control devices corresponding to the switch devices, and configured to sequentially activate one of the switch devices during a test procedure of the testing apparatus (col. 6 lines 15-20 :- IC tester 30 controls auxiliary power supply 38 and the states of switches SW1 and SW2 so that capacitor C2 supplies additional charging current I3 to DUT 34 at the start of each test cycle; col. 11 lines 1-2 :- It should be apparent that probe card 50 may make connections with one DUT as shown in FIG. 18 or a plurality of DUTs, for example, as shown in FIG. 14);
a detection circuit (38,C2), configured to provide a first power supply voltage (+Vc/Vc2) to a first terminal of each of the plurality of switch devices; and
an auxiliary control circuit (36), configured to provide a second power supply voltage (Va/Vb) to a second terminal (junction of R2 & SW2) of each of the plurality of switch devices (SW2) deactivated by the control circuit (30).
Regarding claim 3, Eldridge discloses in figure(s) 1-26 the testing apparatus of Claim 1, wherein the second power supply voltage is higher than the first power supply voltage to compensate a voltage drop caused by a routing path from the auxiliary control circuit to each deactivated switch device (col. 2 lines 25-28 :- a temporary increase in voltage drop across R1 that in turn produces a temporary dip in supply voltage VC below its quiescent level VQ).
Regarding claim 7, Eldridge discloses in figure(s) 1-26 the testing apparatus of Claim 1, wherein each of the switch devices comprises a P-type transistor (Q2 fig. 12).
Regarding claim 8, Eldridge discloses in figure(s) 1-26 the testing apparatus of Claim 7, wherein the P-type transistor (Q2) comprises a gate terminal, electrically connected to a respective selection signal (CNT2) generated by the corresponding control device (30): the first terminal, electrically connected to the first power supply voltage (+Vc/Vc2): the second terminal, selectively connected to the second power supply voltage (Va) or a terminal (Vb) of the corresponding DUT based on the respective selection signal; and a bulk terminal (C2), electrically connected to the first power supply voltage (+Vc).
Regarding claim 9, Eldridge discloses in figure(s) 1-26 the testing apparatus of Claim 8, wherein the first terminal and the second terminal are a source terminal (Q2 source) and a drain terminal (Q2 drain), respectively.
Regarding claim 10, Eldridge discloses in figure(s) 1-26 the testing apparatus of Claim 9, wherein the source terminal and the drain terminal are P-type doped regions formed on a carrier (col. 8 line 35 - transistors Q2 operated in their active regions).
Regarding claim 11, Eldridge discloses in figure(s) 1-26 the testing apparatus of Claim 10, wherein the carrier is an N-type substrate (Q2 - PNP transistor with N-substarte) or an N-type well formed on a P-type substrate.
Regarding claim 14, Eldridge discloses in figure(s) 1-26 a method, comprising:
providing a testing apparatus (testing apparatus of fig. 5) including a plurality of switch devices (SW2) and a plurality of devices under test (DUTs) (34) wherein the switches correspond to the DUTs;
sequentially activating (col. 1 lines 55-60 :- each pulse of the CLOCK signal, there is a temporary increase in the power supply current I1 input to each DUT 14 to provide the charging current necessary to change the switching states of various transistors within the DUT) each of the switch devices of the testing apparatus to test the respective DUT (col. 10 lines 5-10 :- producing output data sequences CNT1, CNT2 and CNT3 that are appropriate for transient current requirements of IC 80 for its expected sequence of states) during a test procedure; and
in response to a specific switch device among the switch devices not being activated, applying a first power supply voltage (+Vc/Vc2) and a second power supply voltage (Va/Vb) to a first terminal and a second terminal of the specific switch device, respectively.
Regarding claim 17, Eldridge discloses in figure(s) 1-26 the method of Claim 14, wherein each of the switch devices comprises a P-type transistor (Q2 fig. 12).
Regarding claim 18, Eldridge discloses in figure(s) 1-26 a testing apparatus, comprising:
a plurality of devices under test (DUTs) (34; fig. 5); and
an advanced process control monitor (APCM), comprising:
a switch circuit, comprising a plurality of switch devices (SW2) corresponding to the DUTs;
a control circuit (30), comprising a plurality of control devices corresponding to the switch devices, and configured to sequentially activate one of the switch devices during a test procedure of the testing apparatus (col. 6 lines 15-20 :- IC tester 30 controls auxiliary power supply 38 and the states of switches SW1 and SW2 so that capacitor C2 supplies additional charging current I3 to DUT 34 at the start of each test cycle);
a detection circuit (38,C2), configured to provide a first power supply voltage (+Vc/Vc2) to a first terminal of each switch device, and to selectively provide a second power supply voltage (Va/Vb) to a second terminal of each switch device deactivated by the control circuit based on a selection signal (CNT2) from the control device (30) corresponding to each switch device (SW2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 15-16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Eldridge in view of Park et al. (US 20230402123).
Regarding claim(s) 2, 19, 15, Eldridge teaches in figure(s) 1-26 the testing apparatus of Claim 1, 18 and the method of claim 14, respectively.
Eldridge does not teach explicitly wherein the first power supply voltage is substantially equal to the second power supply voltage.
However, Park teaches in figure(s) 1-3 wherein the first power supply voltage is substantially equal to the second power supply voltage (external supply VDD and internal supply V_T substantially same in figs. 12,14).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Eldridge by having wherein the first power supply voltage is substantially equal to the second power supply voltage as taught by Park in order to provide "a power manager between the first pad and an input terminal of the first regulator, and between the first pad and the test logic circuit and configured to provide a test power supply voltage to the test logic circuit. In the test mode, while a first target voltage level of the first regulator fluctuates, a second target voltage level of the power manager is maintained constant." (abstract).
Regarding claim 16, Eldridge teaches in figure(s) 1-26 the method of Claim 15, further comprising: in response to the specific switch device being activated, applying the first power supply voltage (+Vc/Vc2) and a voltage (Vb) from the DUT corresponding to the specific switch device (SW2) to the first terminal and the second terminal of the specific switch device, respectively.
Regarding claim 20, Eldridge teaches in figure(s) 1-26 the testing apparatus of Claim 19, wherein each of the switch devices comprises a P-type transistor (Q2) having a gate terminal, electrically connected to the selection signal (CNT2) from the control device corresponding to each switch device; the first terminal, electrically connected to the first power supply voltage (+Vc/Vc2); the second terminal, selectively connected to the second power supply voltage (Va) or a terminal (Vb) of the corresponding DUT based on the respective selection signal (C2); and a bulk terminal, electrically connected to the first power supply voltage (+Vc).
Claim(s) 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Eldridge in view of Goh et al. (US 20150039956).
Regarding claim 4, Eldridge teaches in figure(s) 1-26 the testing apparatus of Claim 1,
Eldridge does not teach explicitly wherein each of the control devices comprises a D flip-flop, and the control devices are connected in series.
However, Goh teaches in figure(s) 1-2 wherein each of the control devices comprises a D flip-flop, and the control devices are connected in series (10*; fig. 2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Eldridge by having wherein each of the control devices comprises a D flip-flop, and the control devices are connected in series as taught by Goh in order to provide applying a known technique to a known device (method, or product) ready for improvement to yield predictable results as evidenced by "flip-flop cell is configured to receive both a test signal and a data input signal and select one of the two to pass to the storage element based on a scan enable signal that indicates either a capture mode or a scan shift mode" (abstract).
Regarding claim 5, Eldridge teaches in figure(s) 1-26 the testing apparatus of Claim 4, wherein when the test procedure of the testing apparatus starts, an input data signal (CNT2) is delivered through the control devices every clock cycle of a clock signal to sequentially activate one of the switch devices (col. 8 lines 18-20 :- produces its output CNT1, CNT2, CNT3 data pattern in response to the same system clock (SYSCLK) that clocks operations of tester 58).
Regarding claim 6, Eldridge teaches in figure(s) 1-26 the testing apparatus of Claim 5, wherein upon the input data signal is delivered to a last one of the control devices, a report voltage signal is asserted (voltage @ fig. 11).
Claim(s) 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Eldridge in view of Wu et al. (US 6872583).
Regarding claim 12, Eldridge teaches in figure(s) 1-26 the testing apparatus of Claim 1,
Eldridge does not teach explicitly wherein the DUTs comprises a first portion and a second portion, and each DUT in the second portion is a dummy device having a particular feature.
However, Wu teaches in figure(s) 1-3 wherein the DUTs (205 fig. 2A) comprises a first portion (112-116; fig. 2A) and a second portion (122-126), and each DUT in the second portion is a dummy device having a particular feature.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Eldridge by having wherein the DUTs comprises a first portion and a second portion, and each DUT in the second portion is a dummy device having a particular feature as taught by Wu in order to provide "Semiconductor chip design and analysis is enhanced by using a dummy structure for analyzing a test structure in a test chip" (abstract).
Regarding claim 13, Eldridge in view of Wu teaches the testing apparatus of Claim 12, wherein the particular feature of each DUT in the second portion forms a particular feature pattern (pattern of 122-126 of Wu in fig. 2A).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JUDY NGUYEN can be reached on 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/Primary Examiner, Art Unit 2858
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