DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/09/2024 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: ENCAPSULATED ELECTRONIC COMPONENT HAVING AN INTERSPERSED ADHESION LAYER AND MANUFACTURING METHOD THEREOF
Claim Objections
Claims 3, 7, 9, and 10 are objected to because of the following informalities:
Claim 3, line 5 should read “the at least one conductor” for consistency of claim terms.
Claim 7, line 7 should read “a first conductor which penetrates” for clarity.
Claim 9, line 2 should read “a first conductor which penetrates” for clarity.
Claim 10, line 2 should read “a first conductor which penetrates” for clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US PGPub 2015/0179616; herein known as Lin).
Regarding claim 1, Lin teaches (Fig. 13) an electronic component, comprising: a first circuit structure (584, [0188]), comprising a topmost conductive layer (542, [0169]); and a chip (534, [0167]), embedded (see recess in figure) in the first circuit structure (584, [0188]) to thermally couple to a portion of the topmost conductive layer of the first circuit structure. The topmost conductive layer of Lin must necessarily thermally couple the chip and first circuit structure of Lin, as it is formed of a conductive material, which necessarily conducts heat.
Regarding claim 3, Lin teaches (Fig. 13) the electronic component of claim 1, further comprising: a second circuit structure (529, [0162]); an encapsulant (568, [0179]); and at least one conductor (532, [0179]), wherein: the chip (534), the conductor (532) and the encapsulant (568) are disposed between the first circuit structure (584) and a second circuit structure (529); and the conductor penetrates ([0179]) through the encapsulant for electrically connecting ([0192]) to the first circuit structure and the second circuit structure ([0192]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 1 above, and further in view of Ramanathan et al. (US PGPub 2020/0194330; herein known as Ramanathan).
Regarding claim 2, Lin teaches the electronic component of claim 1, but does not explicitly teach wherein the topmost conductive layer thermally coupled to the chip is a dummy pattern of the first circuit structure.
Ramanathan teaches (Fig. 2A) wherein the topmost conductive layer (130A, [0031]) thermally coupled to the chip (215, [0028]) is a dummy pattern ([0024, 0031]) of the first circuit structure.
Because Lin and Ramanathan are both directed toward encapsulated chip packages, IWHBO to combine the teachings of Lin and of Ramanathan to include wherein the topmost conductive layer thermally coupled to the chip is a dummy pattern of the first circuit structure in order to improve inter-plane temperature uniformity in the encapsulated device (Ramanathan, [0024]).
Claim 4, 5, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 1 above, and further in view of Wan et al. (US PGPub 2020/0273773; herein known as Wan).
Regarding claim 4, Lin teaches the electronic component of claim 1, but does not explicitly teach further comprising: an adhesion layer, at least filled on the first circuit structure and in contact with the chip.
Wan teaches (Fig. 1E) an adhesion layer (TA1, [0027]), at least filled on the first circuit structure (110, [0049]) and in contact with the chip (130, [0027]).
Because Lin and Wan are both directed toward encapsulated packages, IWHBO to combine the teachings of Lin and of Wan to include an adhesion layer, at least filled on the first circuit structure and in contact with the chip, in order to provide stability during and after the packaging process.
Regarding claim 5, Lin in view of Wan teaches (Wan, Fig. 1E) the electronic component of claim 4, wherein a portion of the adhesion layer (TA1, [0027]) is disposed between the chip (130, [0033]) and the first circuit structure (110, [0049]).
Regarding claim 7, Lin in view of Wan teaches (Lin, Fig. 13) the electronic component of claim 4, further comprising: further comprising: a second circuit structure (529, [0162]); an encapsulant (568, [0179]); and at least one conductor (532, [0179]), wherein: the chip (534), the conductor (532) and the encapsulant (568) are disposed between the first circuit structure (584) and a second circuit structure (529); and the conductor penetrates ([0179]) through the encapsulant for electrically connecting ([0192]) to the first circuit structure and the second circuit structure ([0192]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Wan as applied to claim 4 above, and further in view of Pendse et al. (US PGPub 2022/0328740; herein known as Pendse).
Regarding claim 10, Lin in view of Wan teaches (Lin, Fig. 13) the electronic component of claim 7, wherein the at least one conductor (532, [0179]) further comprises a second conductor (multiple conductors shown) penetrates through the encapsulant (568, [0179]) but does not explicitly teach for thermally coupling to the chip, and wherein the second conductor is a dummy conductor.
Pendse teaches a second conductor (1318, [0188]) for thermally coupling to the chip (1300, [0188]) and wherein the second conductor is a dummy conductor ([0188]).
Because Lin in view of Wan and Pendse are directed toward encapsulated packages, IWHBO to combine the teachings of Lin in view of Wan and of Pendse in order to increase the effective thermal conductivity of the chip.
Claims 11, 12, 13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin.
Regarding claim 11, Lin teaches (Fig. 13) an electronic component, comprising: a first circuit structure (584, [0188]), comprising a conductive routing (542, [0169]); a second circuit structure (529, [0162]); a chip (534, [0167]), having an active surface (538, [0179]) disposed between the first circuit structure (584) and the second circuit structure (529); an encapsulant (568, [0179]), disposed between the first circuit structure (584) and the second circuit structure (529), and laterally surrounding the chip ([0179]); and a first conductor (532, [0179]), penetrating through the encapsulant for electrically connecting to the first circuit structure and the second circuit structure ([0179]), wherein: a portion of the conductive routing of the first circuit structure thermally coupled to the chip. The conductive routing of Lin must necessarily thermally couple the chip and first circuit structure of Lin, as it is formed of a conductive material, which necessarily conducts heat.
Lin does not explicitly teach having an active surface facing the second circuit structure.
In an additional embodiment, Lin teaches (Fig. 20) an active surface (830, [0254]) facing the second circuit structure (884, [0279]).
IWHBO to combine the embodiments of Lin to include having an active surface facing the second circuit structure in order to take advantage of minimized manufacturing steps by completing a build-up process without a flip step.
Regarding claim 12, Lin teaches (annotated Fig. 13 below) the electronic component of claim 11, wherein: the first circuit structure (584) has a first side (S1) and a second side (S2) opposite the first side; and the portion of the conductive routing (542) thermally coupling to the chip continually extends from the first side to the second side of the first circuit structure. The term "continually" is interpreted to be defined as implemented in an interval fashion (e.g. having more than one separated portion extending across a distance).
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Regarding claim 13, Lin teaches (Fig. 13) the electronic component of claim 11, wherein: the first circuit structure has a first side (S1) and a second side (S2) opposite the first side; and the portion (582, [0187]) of the conductive routing thermally coupling to the chip protrudes on the first side. See Figure.
Regarding claim 16, Lin teaches (Fig. 13) the electronic component of claim 11, wherein the chip (534) is embedded in the first circuit structure (584). See Figure.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Pendse.
Regarding claim 14, Lin teaches (Fig. 13) the electronic component of claim 11, further comprising: a second conductor (multiple conductors shown), penetrating through the encapsulant (568, [0179]) but does not explicitly teach to contact the portion of the conductive routing of the first circuit structure for thermally coupling to the chip.
Pendse teaches a second conductor (1318, [0188]) to contact the portion of the conductive routing of the first circuit structure for thermally coupling to the chip (1300, [0188]).
Because Lin in view of Wan and Pendse are directed toward encapsulated packages, IWHBO to combine the teachings of Lin in view of Wan and of Pendse in order to increase the effective thermal conductivity of the chip.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Ramanathan.
Regarding claim 15, Lin teaches the electronic component of claim 11, but does not explicitly teach wherein the portion of the conductive routing of the first circuit structure thermally coupled to the chip is a dummy structure.
Ramanathan teaches (Fig. 2A) the portion of the conductive routing of the first circuit structure (130A, [0031]) thermally coupled to the chip (215, [0028]) is a dummy structure ([0024, 0031]).
Because Lin and Ramanathan are both directed toward encapsulated chip packages, IWHBO to combine the teachings of Lin and of Ramanathan to include wherein the portion of the conductive routing of the first circuit structure thermally coupled to the chip is a dummy structure. in order to improve inter-plane temperature uniformity in the encapsulated device (Ramanathan, [0024]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Tseng et al. (US PGPub 2020/0381363; herein known as Tseng).
Regarding claim 17, Lin teaches the electronic component of claim 11, but does not explicitly teach further comprising: a conductive terminal, disposed on the first circuit structure for thermally coupling to the chip.
Tseng teaches (Fig. 11) a conductive terminal (158, [0039]), disposed on the first circuit structure for thermally coupling to the chip ([0039]).
Because Lin and Tseng are both directed toward encapsulated chip structures, IWHBO to combine the teachings of Lin and of Tseng to include a conductive terminal, disposed on the first circuit structure for thermally coupling to the chip. in order to provide external dissipation of heat from the package substrate ([0039]).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Wan.
Regarding claim 18, Lin teaches (Fig. 13) a method, comprising: providing a first circuit structure (564, [0188]) having a recess (see figure); forming at least one conductor (542, [0169]) on the first circuit structure; configuring a chip (534, [0167]) on the first circuit structure corresponding to the recess (formed over the recess); forming an encapsulant (568, [0190]) on the first circuit structure; and forming a second circuit structure (529, [0192]) on the encapsulant, but does not explicitly teach forming an adhesion layer on the first circuit structure corresponding to the recess.
Wan teaches (Fig. 1E) an adhesion layer (TA1, [0027]) on the first circuit structure (110, [0049]) corresponding to the recess.
Because Lin and Wan are both directed toward encapsulated packages, IWHBO to combine the teachings of Lin and of Wan to include forming an adhesion layer on the first circuit structure corresponding to the recess, in order to provide stability during and after the packaging process.
Regarding claim 19, Lin in view of Wan teaches (Lin, Fig. 13) the method of claim 18, further comprising: forming a filling layer on the adhesion layer (not pictured, [0213]).
Regarding claim 20, Lin in view of Wan teaches (Lin, Fig. 13) the method of claim 18, wherein a removal process ([0078]) is performed to expose a portion of a conductive layer ([0078]) for forming the first circuit structure having the recess.
Allowable Subject Matter
Claims 6, 8, and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, the electronic component of claim 1, wherein a portion of the adhesion layer laterally covers a side wall of the topmost conductive layer thermally coupled to the chip. Lin in view of Wan teaches wherein an adhesive layer is disposed over the topmost conductive layer, but does not teach nor suggest wherein the adhesive layer would be disposed over sidewalls of the topmost conductive layer. Lin teaches a dielectric material covering the sidewall of the topmost conductive layer, which one of ordinary skill in the art would not be motivated to replace with an adhesive layer, which would not provide adequate electrical isolation as a replacement material.
Regarding claim 8, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, the electronic component of claim 7, wherein the first conductor further penetrates through the adhesion layer. Lin in view of Wan teaches a first conductor and an adhesion layer, but the adhesion layer is disposed solely under the semiconductor chip, and is not disposed under the conductor portion of the device. One of ordinary skill in the art would not have been motivated to include the adhesion material under the external routing area, as it would interrupt manufacturing processes (dielectric fill, via routing, etc) in those areas.
Regarding claim 9, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, the electronic component of claim 7 wherein a second conductor penetrates through the adhesion layer. Lin in view of Wan teaches a first conductor and an adhesion layer, but the adhesion layer is disposed solely under the semiconductor chip, and is not disposed under the conductor portion of the device. One of ordinary skill in the art would not have been motivated to include the adhesion material under the external routing area, as it would interrupt manufacturing processes (dielectric fill, via routing, etc) in those areas.
Prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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