DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 15- 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 2019/0214473) (hereafter Xie).
Regarding claim 15, Xie discloses an integrated chip (IC), comprising:
a first semiconductor fin (213 and 204 in Fig. 13B, paragraph 0061) protruding from a semiconductor substrate 201 (Fig. 13B, paragraph 0043);
a second semiconductor fin 212 (Fig. 13B, paragraph 0048) protruding from the semiconductor substrate 201 (Fig. 13B);
a third semiconductor fin 211 (Fig. 13B, paragraph 0048) protruding from the semiconductor substrate 201 (Fig. 13B) and having a top surface recessed relative to lower than a top surface of the first semiconductor fin (213 and 204 in Fig. 13B), wherein the first (213 and 204 in Fig. 13B), second 212 (Fig. 13B), and third semiconductor fins 211 (Fig. 13B) are laterally spaced from each other in a first direction (horizontal direction in Fig. 13B);
a first nanostructure stack 11 (Fig. 13B, paragraph 0066) directly over and spaced from the third semiconductor fin 211 (Fig. 13B), wherein the first nanostructure stack 11 (Fig. 13B) comprises a plurality of first semiconductor nanostructures 11 (Fig. 13B, paragraph 0074, wherein “nanowire (NW) channel region”);
a first gate electrode 33 (Fig. 13B, paragraph 0067) overlying (see Fig. 13B, wherein 33 is located higher than 213, 204, 212, and 211) the first (213 and 204 in Fig. 13B), second 212 (Fig. 13B), and third semiconductor fins 211 (Fig. 13B); and
a second gate electrode 13 (Fig. 13C, paragraph 0067) overlying (see Fig. 13B, wherein 13 is located higher than 213, 204, 212, and 211) the first 213 (Fig. 13C) and third semiconductor fins 211 (Fig. 13C), laterally offset from the second semiconductor fin 212 (Fig. 13C), and laterally spaced from the first gate electrode 33 (Fig. 13C) in a second direction (horizontal direction in Fig. 13C) transverse (see Fig. 13A) to the first direction (horizontal direction in Fig. 13B).
Regarding claim 16, Xie further discloses the IC according to claim 15, wherein the second semiconductor fin 212 (Fig. 13B) is laterally between the first (213 and 204 in Fig. 13B) and third semiconductor fins 211 (Fig. 13B) in the first direction (horizontal direction in Fig. 13B).
Regarding claim 17, Xie further discloses the IC according to claim 15, further comprising: a second nanostructure stack 21 (Fig. 13B, paragraph 0075, wherein “nanosheet (NS) channel region”) directly over and spaced from the second semiconductor fin 212 (Fig. 13B), wherein the second nanostructure stack 21 (Fig. 13B) comprises a plurality of second semiconductor nanostructures 21 (Fig. 13B) that are stacked.
Regarding claim 18, Xie further discloses the IC according to claim 15, further comprising: a pair of first source/drain regions (left 32 and 22 in Fig. 13C, paragraph 0070) between which the first gate electrode 33 (Fig. 13C) is arranged, wherein the pair of first source/drain regions (left 32 and 22 in Fig. 13C) overlie and are directly on the first (213 in Fig. 13C) and second semiconductor fins (212 in Fig. 13C); and
a pair of second source/drain regions (right 32 and 12 in Fig. 13C, paragraph 0070) between which the second gate electrode 13 (Fig. 13C) is arranged, wherein the pair of second source/drain regions (right 32 and 12 in Fig. 13C) overlie and are directly on the first semiconductor fin (213 in Fig. 13C), and wherein the pair of second source/drain regions (right 32 and 12 in Fig. 13C) are spaced from the second semiconductor fin (212 in Fig. 13C).
Regarding claim 19, Xie further discloses the IC according to claim 18, wherein the pair of first source/drain regions (left 32 and 22 in Fig. 13C) have individual widths (longest widths of left 32 and 22 in Fig. 13C) in the first direction that are greater than individual widths (shortest widths of left 32 and 22 in Fig. 13C) of the pair of second source/drain regions (right 32 and 12 in Fig. 13C) in the first direction.
Regarding claim 20, Xie further discloses the IC according to claim 15, wherein the first nanostructure stack 11 (Fig. 13C) has a first width (width of 11 in Fig. 13C) at the first gate electrode and has a second width (width of 11 in Fig. 13B) at the second gate electrode 13 (Fig. 13B), and wherein the second width (see Figs. 13B and 13C) is less than the first width.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6,and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2019/0214473) (hereafter Xie), in view of Chiang et al. (US 2019/0355724) (hereafter Chiang).
Regarding claim 1, Xie discloses an integrated chip (IC), comprising:
a first semiconductor fin (213 and 204 in Fig. 13B, paragraph 0061) projecting vertically from a semiconductor substrate 201 (Fig. 13B, paragraph 0043);
a second semiconductor fin 211 (Fig. 13B, paragraph 0048) projecting vertically from the semiconductor substrate 201 (Fig. 13B), wherein the second semiconductor fin 211 (Fig. 13B) has a lesser height than the first semiconductor fin (213 and 204 in Fig. 13B) and is laterally spaced from the first semiconductor fin (213 and 204 in Fig. 13B);
a first nanostructure stack 11 (Fig. 13B, paragraph 0074) directly over and spaced from the second semiconductor fin 211 (Fig. 13B), wherein the first nanostructure stack 11 (Fig. 13B) comprises a plurality of first semiconductor nanostructures 11 (Fig. 13B);
a pair of first source/drain regions 32 (Fig. 13C, paragraph 0076) overlying the first semiconductor fin (213 and 31 in Fig. 13C);
a pair of second source/drain regions 12a (Fig. 13D, paragraph 0074) overlying the second semiconductor fin 211 (Fig. 13D); and
a gate electrode (13, 23, and 33 in Fig. 13C, paragraph 0067) between (see Fig. 13C, wherein 33 is between 32) and bordering the pair of first source/drain regions 32 (Fig. 13C).
Xie does not disclose a gate electrode between and bordering the pair of first source/drain regions, between and bordering the pair of second source/drain regions, and continuous from directly over the first semiconductor fin to directly over the second semiconductor fin.
Chiang discloses a gate electrode 1087 (Fig. 25A, paragraph 0062) between and bordering the pair of first source/drain regions (element number is not shown in Fig. 25D but see 1039 in Fig. 17D, paragraph 0056), between and bordering the pair of second source/drain regions (element number is not shown in Fig. 25 but see 1039 in Fig. 17C, paragraph 0056), and continuous from directly over the first semiconductor fin (element number is not shown in Fig. 25A but see right vertical portion of 600 and 1024’ in Fig. 9B) to directly over the second semiconductor fin (element number is not shown in Fig. 25A but see left vertical portion of 600 in Fig. 9B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie to form a gate electrode between and bordering the pair of first source/drain regions, between and bordering the pair of second source/drain regions, and continuous from directly over the first semiconductor fin to directly over the second semiconductor fin, as taught by Chiang, since a new hybrid design (Chiang, paragraph 0035) of the MuGFET which solves the area penalty caused by the n/p boundary.
Regarding claim 2, Xie further discloses the IC according to claim 1, wherein the gate electrode (13, 23, and 33 in Fig. 13B) extends in a closed path around each of the plurality of first semiconductor nanostructures 11 (Fig. 13B).
Regarding claim 3, Xie further discloses the IC according to claim 1, wherein the first semiconductor fin (213 and 204 in Fig. 13B), the pair of first source/drain regions 32 (Fig. 13C), and a first portion 33 (Fig. 13B) of the gate electrode (13, 23, and 33 in Fig. 13B) form a fin field-effect transistor (FinFET) (“FINFET Area” in Fig. 13B), and wherein the second semiconductor fin 211 (Fig. 13B), the pair of second source/drain regions 12 (Fig. 13C), and a second portion 13 (Fig. 13B) of the gate electrode (13, 23, and 33 in Fig. 13B) form a gate-all- around field-effect transistor (GAAFET) (“GAAFETs” in paragraph 0046).
Regarding claim 6, Xie further discloses the IC according to claim 1, further comprising: a third semiconductor fin 212 (Fig. 13B, paragraph 0048) projecting vertically from the semiconductor substrate 201 (Fig. 13B), wherein the pair of first source/drain regions 22 (Fig. 13C) overlie the third semiconductor fin 212 (Fig. 13C).
Regarding claim 7, Xie further discloses the IC according to claim 1, further comprising: a third semiconductor fin 212 (Fig. 13B, paragraph 0048) projecting vertically from the semiconductor substrate 201 (Fig. 13B), wherein the pair of second source/drain regions 22 (Fig. 13C) overlie the third semiconductor fin 212 (Fig. 13B); and a second nanostructure stack 21 (Fig. 13B, paragraph 0075) directly over and spaced from the third semiconductor fin 212 (Fig. 13B), wherein the second nanostructure stack 21 (Fig. 13B) comprises a plurality of second semiconductor nanostructures 21 (Fig. 13B) that are vertically stacked.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Xie, in view of Chiang as applied to claim 1 above, and further in view of Leobandung (US 2019/0214409) (hereafter Leobandung).
Regarding claim 4, Xie in view of Chiang discloses the IC according to claim 1, however Xie and Chiang do not disclose the first semiconductor fin has a first lattice orientation at a top of the first semiconductor fin, and wherein the plurality of first semiconductor nanostructures have a second lattice orientation that is different than the first lattice orientation.
Leobandung discloses the first semiconductor fin (upper portion of 104 between 116 in Fig. 13C) has a first lattice orientation (see “<110> orientation” in paragraph 0093; see Fig. 4B and paragraph 0063, wherein 106 and 108 are epitaxially grown from 104; and see paragraph 0072, wherein 120a and 120b are epitaxially grown from 106 and 108 such that 104 has same lattice orientation as 120a and 120b) at a top of the first semiconductor fin (upper portion of 104 between 116 in Fig. 13C), and wherein the plurality of first semiconductor nanostructures 106 (Fig. 13C, paragraph 0093) have a second lattice orientation (see “<100> orientation” in paragraph 0093) that is different than the first lattice orientation (see “<110> orientation” in paragraph 0093).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie to form the first semiconductor fin has a first lattice orientation at a top of the first semiconductor fin, and wherein the plurality of first semiconductor nanostructures have a second lattice orientation that is different than the first lattice orientation, as taught by Leobandung, since the fin-type PFET 202 (Leobandung, Fig. 13C, paragraph 0093) has a <110> orientation that optimizes hole mobility through the fins 120a and 120b (i.e., the PFET channels) (Leobandung, Fig. 13C, paragraph 0093), while the nanosheet NFET 204 (Leobandung, Fig. 13C, paragraph 0093) has a <100> orientation that optimizes electron mobility through the individual nanosheets 106 (i.e., the NFET channels) (Leobandung, Fig. 13C, paragraph 0093) such that the entire performance of the CMOS device 200 (Leobandung, Fig. 13A, paragraph 0093) fabricated from the process flow described herein is optimized compared to conventional CMOS devices.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Xie, in view of Chiang as applied to claim 1 above, and further in view of Lin et al. (US 2021/0126110) (hereafter Lin).
Regarding claim 5, Xie in view of Chiang discloses the IC according to claim 1, however Xie and Chiang do not disclose a pair of dummy gates that are continuous from directly over the first semiconductor fin to directly over the second semiconductor fin, wherein the pair of first source/drain regions are between and respectively border the pair of dummy gates, and wherein the pair of second source/drain regions are between and respectively border the pair of dummy gates.
Lin discloses a pair of dummy gates (62 of 100FE in Fig. 12; see 100FE in Fig. 6B; and see Fig. 4B and paragraph 0024, wherein “ Similarly, on the left ends (not shown) of protruding fins 36, there may also be a dummy gate stack 38B (not shown) covering the left edge portions of dummy gate stacks 38B”) that are continuous from directly over the first semiconductor fin (top 36 in Fig. 6B, paragraph 0024) to directly over the second semiconductor fin (bottom 36 in Fig. 6B, paragraph 0024), wherein the pair of first source/drain regions (top portions of right 54 and middle 54 in Fig. 6B) are between and respectively border the pair of dummy gates, and wherein the pair of second source/drain regions (bottom portions of right 54 and middle 54 in Fig. 6B) are between and respectively border the pair of dummy gates.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie to form a pair of dummy gates that are continuous from directly over the first semiconductor fin to directly over the second semiconductor fin, wherein the pair of first source/drain regions are between and respectively border the pair of dummy gates, and wherein the pair of second source/drain regions are between and respectively border the pair of dummy gates, as taught by Lin, since keeping the dielectric layer 40 (Lin, Fig. 12, paragraph 0045) to be left in device region 100FE (Lin, Fig. 12, paragraph 0045) has the function of protecting the underlying end portions 36B (Lin, Fig. 12, paragraph 0045) of protruding fin 36 (Lin, Fig. 12, paragraph 0045), and protecting neighboring source/drain regions.
Claims 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2019/0214473) (hereafter Xie), in view of Lin et al. (US 2021/0126110) (hereafter Lin).
Regarding claim 8, Xie discloses an integrated chip (IC), comprising:
a first semiconductor fin (213 and 204 in Fig. 13B, paragraph 0061) protruding from a semiconductor substrate 201 (Fig. 13B, paragraph 0043);
a second semiconductor fin 211 (Fig. 13B, paragraph 0048) protruding from the semiconductor substrate 201 (Fig. 13B) and laterally spaced from the first semiconductor fin (213 and 204 in Fig. 13B) in a first direction (vertical direction in Fig. 13B);
a nanostructure stack (11 and 21 in Fig. 13B, paragraph 0074) directly over and spaced from the second semiconductor fin 211 (Fig. 13B), wherein the nanostructure stack (11 and 21 Fig. 13B) has a bottom surface recessed relative to lower than a top surface of the first semiconductor fin (213 and 204 in Fig. 13B) and comprises a plurality of semiconductor nanostructures (11 and 21 in Fig. 13B);
a first gate electrode 33 (Fig. 13B, paragraph 0067) overlying (see Fig. 13B, wherein 33 located higher than 204 and 211) the first (213 and 204 in Fig. 13B) and second semiconductor fins 211 (Fig. 13B); and
a second gate electrode 13 (Fig. 13B, paragraph 0067) overlying the first (213 and 204 in Fig. 13B) and second semiconductor fins 211 (Fig. 13B) and laterally spaced from the first gate electrode 33 (Fig. 13B) in a second direction (horizontal direction in Fig. 13B) transverse to the first direction (vertical direction in Fig. 13B);
wherein the second semiconductor fin 211 (Fig. 13B) has a first width (horizontal length of 211 in Fig. 13B) directly under the first gate electrode 33 (Fig. 13B).
Xie does not disclose the second semiconductor fin has a second width directly under the second gate electrode, and wherein the first and second widths extend in the first direction and are different from each other.
Lin discloses the second semiconductor fin (middle 36’ in Fig. 15, paragraph 0047) has a second width (similar to horizontal width of vertical portion of 20 of 100FE in Fig. 22A; and see a portion of the middle 36’ overlapping with rightmost 38 in Fig. 15) directly under the second gate electrode 72B (Fig. 22A, paragraph 0039), and wherein the first (horizontal width of vertical portion of 20 of 100C in Fig. 22A; and see a portion of the top 36’ overlapping with middle 38 in Fig. 15) and second widths (horizontal width of vertical portion of 20 of 100FE in Fig. 22A) extend in the first direction (horizontal direction in Fig. 22A) and are different from each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie to form the second semiconductor fin has a second width directly under the second gate electrode, and wherein the first and second widths extend in the first direction and are different from each other, as taught by Lin, since the remaining dielectric layers (Lin, paragraph 0055) on the fin-end portions of the protruding fins protect the end portions of the protruding fins from being damaged, and the end portions of the protruding fins may further protect the neighboring source/drain regions.
Regarding claim 9, Xie further discloses the IC according to claim 8, wherein the first 33 (Fig. 13B) and second gate electrodes 13 (Fig. 13B) directly overlie the nanostructure stack (11 and 21 in Fig. 13B).
Regarding claim 10, Xie further discloses the IC according to claim 8, further comprising: a dummy gate (33 contacting 205 of 30 in Fig. 13C) overlying the first 213 (Fig. 13C) and second semiconductor fins 211 (Fig. 13C), laterally between the first 33 (Fig. 13C) and second gate electrodes 13 (Fig. 13C) in the second direction, wherein the second semiconductor fin 211 (Fig. 13C) discretely changes from the first width to the second width directly under the dummy gate (33 contacting 205 of 30 in Fig. 13C).
Regarding claim 11, Xie further discloses the IC according to claim 8, further comprising: a third semiconductor fin 212 (Fig. 13B, paragraph 0048) protruding from the semiconductor substrate 201 (Fig. 13B) and laterally between the first (213 and 204 in Fig. 13B) and second semiconductor fins 211 (Fig. 13B) in the first direction, wherein the first gate electrode 33 (Fig. 13B) overlies the third semiconductor fin 212 (Fig. 13B), and wherein the second gate electrode 13 (Fig. 13B) is laterally offset from the third semiconductor fin 212 (Fig. 13B) in the second direction.
Regarding claim 12, Xie further discloses the IC according to claim 11, wherein the first width (horizontal length of 213 in Fig. 13C) is greater than the second width (horizontal length of 211 in Fig. 13B).
Regarding claim 13, Xie further discloses the IC according to claim 8, further comprising: a pair of first source/drain regions 32 (Fig. 13C, paragraph 0076) overlying the second semiconductor fin 211 (Fig. 13C) and between which the first gate electrode 33 (Fig. 13C) is laterally sandwiched; and a pair of second source/drain regions 12 (Fig. 13C, paragraph 0074) overlying the second semiconductor fin 211 (Fig. 13C) and between which the second gate electrode 13 (Fig. 13C) is laterally sandwiched; wherein the pair of first source/drain regions 32 (Fig. 13C) have individual widths (longest horizontal length of 32 in Fig. 13C) greater than individual widths (shortest horizontal length of 32 in Fig. 13C) of the pair of second source/drain regions 12 (Fig. 13C).
Regarding claim 14, Xie further discloses the IC according to claim 8, wherein the first semiconductor fin (213 and 204 in Fig. 13B) has a third width directly under the first gate electrode 33 (Fig. 13B) and has a fourth width directly under the second gate electrode 13 (Fig. 13B), and wherein the third and fourth widths (Fig. 13B) are less than the first and second widths (Fig. 13C).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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