Attorney’s Docket Number: 2519-0557PUS3
Filing Date: 04/09/2024
Claimed Priority Date: 06/01/2022 (CON of 17/829,950 now PAT 11984355)
09/11/2020 (CON of 17/018,733 now PAT 11488861)
09/14/2017 (DIV of 15/704,202 now PAT 10777452)
Applicants: Ho et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 08/05/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Species 7 (drawn to Fig. 9), in the reply filed on 08/05/2026, is acknowledged. Applicant cancelled claim 11, added new claim 21, and indicated that claims 1-10 and 12-21 read on the elected Species. The examiner agrees. Accordingly, pending in this application are claims 1-10 and 12-21.
Specification
The disclosure is objected to because of the following informalities:
- Par. [0026], L. 2: amend to -- the ESL 118 in this case--, in accordance with Par. [0025], L. 2 reciting “an etch stop layer (ESL) 118” and Fig. 1A.
Appropriate correction is required.
Claim Objections
Claim13 is objected to because of the following informalities:
- L 1-2: amend to -- wherein the second dielectric layer has a portion vertically overlapping the conductive element--, for clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8-10, 12-13, 15-17, and 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Streck et al. (US2010/0025855).
Regarding Claim 8, Streck (see, e.g., Fig. 2k and Par. [0042]) shows all aspects of the instant invention, including an interconnect structure, comprising:
- a first dielectric layer (e.g., dielectric material 211)
- a conductive element (e.g., metal region 212) in the first dielectric layer
- a second dielectric layer (e.g., dielectric material 231) over the first dielectric layer
- a bottom via (e.g., portion 235V in opening 231V) in the second dielectric layer and in contact with a top surface of the conductive element
- a dielectric spacer (e.g., dielectric material layer 233) lining a first sidewall of the bottom via, wherein the dielectric spacer is in contact with a top surface of the first dielectric layer (e.g., material of 233 fills void 211A and contacts top surface of 211)
Regarding Claim 9, Streck (see, e.g., Fig. 2k and Par. [0042]) shows that the dielectric spacer (e.g., 233) is in contact with the second dielectric layer (e.g., 231).
Regarding Claim 10, Streck (see, e.g., Fig. 2k and Par. [0042]) shows a top via (e.g., portion 235T in opening 231V) over and electrically connected with the bottom via, wherein the top via is wider than the bottom via.
Regarding Claim 13, Streck (see, e.g., Fig. 2k and Par. [0042]) shows that the second dielectric layer (e.g., 231) has a portion vertically overlaps the conductive element (e.g., 212).
Regarding Claim 15, Streck (see, e.g., Fig. 2k and Par. [0042]) shows an etch stop layer (e.g., etch stop layer 113/213) between the first dielectric layer (e.g., 211) and the second dielectric layer (e.g., 231), wherein the etch stop layer is in contact with the dielectric spacer (e.g., 233).
Regarding Claim 16, Streck (see, e.g., Fig. 2k and Par. [0042]) shows all aspects of the instant invention, including an interconnect structure, comprising:
- a first dielectric layer (e.g., dielectric material 211)
- a conductive element (e.g., metal region 212) in the first dielectric layer
- a second dielectric layer (e.g., dielectric material 231) over the first dielectric layer
- a bottom via (e.g., portion 235V in opening 231V) in the second dielectric layer and in contact with a top surface of the conductive element
- a dielectric spacer (e.g., dielectric material layer 233) lining a sidewall of the bottom via, wherein a bottom surface of the dielectric spacer is lower than a top surface of the first dielectric layer (e.g., material of 233 fills void 211A and has a bottom surface lower than a top surface of 211)
Regarding Claim 17, Streck (see, e.g., Fig. 2k and Par. [0042]) shows an etch stop layer (e.g., etch stop layer 113/213) between the first dielectric layer (e.g., 211) and the second dielectric layer (e.g., 231), wherein the bottom surface of the dielectric spacer is lower than a bottom surface of the etch stop layer (e.g., 233 has a bottom surface lower than a bottom surface of 213).
Regarding Claim 20, Streck (see, e.g., Fig. 2k and Par. [0042]) shows that the sidewall of the bottom via (e.g., 235V) is spaced apart from the second dielectric layer (e.g., 231) through the dielectric spacer (e.g., 233).
Regarding Claim 21, Streck (see, e.g., Fig. 2k and Par. [0042]) shows that the bottom surface of the dielectric spacer is lower than a top surface of the conductive element (e.g., 233 has a bottom surface lower than a top surface of 212).
Regarding Claim 8, Streck (see, e.g., Fig. 2j and Par. [0041]) shows all aspects of the instant invention, including an interconnect structure, comprising:
- a first dielectric layer (e.g., dielectric material 211)
- a conductive element (e.g., metal region 212) in the first dielectric layer
- a second dielectric layer (e.g., dielectric material 231) over the first dielectric layer
- a bottom via (e.g., portion 235V in opening 231V) in the second dielectric layer and in contact (e.g., electrical contact) with a top surface of the conductive element
- a dielectric spacer (e.g., dielectric material layer 233) lining a first sidewall of the bottom via, wherein the dielectric spacer is in contact with a top surface of the first dielectric layer (e.g., material of 233 contacts top surface of 211)
Regarding Claim 9, Streck see, e.g., Fig. 2j and Par. [0041]) shows that the dielectric spacer (e.g., 233) is in contact with the second dielectric layer (e.g., 231).
Regarding Claim 10, Streck see, e.g., Fig. 2j and Par. [0041]) shows a top via (e.g., portion 235T in opening 231V) over and electrically connected with the bottom via, wherein the top via is wider than the bottom via.
Regarding Claim 12, Streck (see, e.g., Fig. 2j and Par. [0041]) shows a barrier layer (e.g., barrier material 235A) lining the top via, wherein the barrier layer is in contact with the bottom via and the dielectric spacer.
Regarding Claim 13, Streck (see, e.g., Fig. 2j and Par. [0041]) shows that the second dielectric layer (e.g., 231) has a portion vertically overlaps the conductive element (e.g., 212).
Regarding Claim 15, Streck (see, e.g., Fig. 2j and Par. [0041]) shows an etch stop layer (e.g., etch stop layer 113/213) between the first dielectric layer (e.g., 211) and the second dielectric layer (e.g., 231), wherein the etch stop layer is in contact with the dielectric spacer (e.g., 233).
Claims 8-10, 13, 16, and 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Edelstein et al. (US2017/0170113).
Regarding Claim 8, Edelstein (see, e.g., Fig. 8 and Par. [0020]-[0027]) shows all aspects of the instant invention, including an interconnect structure, comprising:
- a first dielectric layer (e.g., insulator layer 102)
- a conductive element (e.g., comprising interconnect structure 106 and metal diffusion barrier layer 108) in the first dielectric layer
- a second dielectric layer (e.g., dielectric layer 112) over the first dielectric layer
- a bottom via (e.g., bottom portion of interconnect structure 118) in the second dielectric layer and in contact with a top surface of the conductive element
- a dielectric spacer (e.g., nitridized insulating layer 116) lining a first sidewall of the bottom via, wherein the dielectric spacer is in contact with a top surface of the first dielectric layer (e.g., 102) (see, e.g., Fig. 7A and Par. [0030])
Regarding Claim 9, Edelstein (see, e.g., Fig. 8 and Par. [0020]-[0027]) shows that the dielectric spacer (e.g., 116) is in contact with the second dielectric layer (e.g., 112).
Regarding Claim 10, Edelstein (see, e.g., Fig. 8 and Par. [0020]-[0027]) shows a top via (e.g., bottom portion of interconnect structure 118) over and electrically connected with the bottom via, wherein the top via is wider than the bottom via.
Regarding Claim 13, Edelstein (see, e.g., Fig. 8 and Par. [0020]-[0027]) shows that the second dielectric layer (e.g., 112) has a portion vertically overlaps the conductive element (e.g., 106,108).
Regarding Claim 16, Edelstein (see, e.g., Fig. 8 and Par. [0020]-[0027]) shows all aspects of the instant invention, including an interconnect structure, comprising:
- a first dielectric layer (e.g., insulator layer 102)
- a conductive element (e.g., comprising interconnect structure 106 and metal diffusion barrier layer 108) in the first dielectric layer
- a second dielectric layer (e.g., dielectric layer 112) over the first dielectric layer
- a bottom via (e.g., bottom portion of interconnect structure 118) in the second dielectric layer and in contact with a top surface of the conductive element
- a dielectric spacer (e.g., nitridized insulating layer 116) lining a sidewall of the bottom via, wherein a bottom surface of the dielectric spacer is lower than a top surface of the first dielectric layer (e.g., 102) (see, e.g., Fig. 7A and Par. [0030])
Regarding Claim 20, Edelstein (see, e.g., Fig. 8 and Par. [0020]-[0027]) shows that the sidewall of the bottom via is spaced apart from the second dielectric layer (e.g., 112) through the dielectric spacer (e.g., 116).
Regarding Claim 21, Edelstein (see, e.g., Fig. 8 and Par. [0020]-[0027]) shows that the bottom surface of the dielectric spacer (e.g., 116) is lower than a top surface of the conductive element (e.g., 106,108).
Claims 1-3, 6, 8-10, 13-14, and 16-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US2017/0256444).
Regarding Claim 1, Chang (see, e.g., Fig. 2) shows all aspects of the instant invention, including an interconnect structure, comprising:
- a first dielectric layer (e.g., dielectric layer 108)
- a conductive element (e.g., gate stack 111 comprising gate electrode 112) in the first dielectric layer
- a second dielectric layer (e.g., dielectric layer 118) over the first dielectric layer
- a bottom via (e.g., bottom portion of connector 122) in the second dielectric layer and in contact with a top surface of the conductive element, wherein a first sidewall of the bottom via (e.g., left sidewall) is in contact with the second dielectric layer
- a dielectric spacer (e.g., shielding layer 116 or spacer 104) lining a second sidewall of the bottom via (e.g., right sidewall) opposite to the first sidewall of the bottom via, wherein the second sidewall of the bottom via is spaced apart from the second dielectric layer through the dielectric spacer.
Regarding Claim 2, Chang (see, e.g., Fig. 2) shows that the dielectric spacer (e.g., 116 or 104) is in contact with the first dielectric layer (e.g., 108).
Regarding Claim 3, Chang (see, e.g., Fig. 2) shows a top via (e.g., top portion of connector 122) over and electrically connected with the bottom via, wherein the top via vertically overlaps the dielectric spacer (e.g., 116 or 104).
Regarding Claim 6, Chang (see, e.g., Fig. 2) shows an etch stop layer (e.g., shielding layer 116) between the first dielectric layer (e.g., 108) and the second dielectric layer (e.g., 118), wherein the etch stop layer is in contact with the dielectric spacer (e.g., spacer 104).
Regarding Claim 8, Chang (see, e.g., Fig. 2) shows all aspects of the instant invention, including an interconnect structure, comprising:
- a first dielectric layer (e.g., dielectric layer 108)
- a conductive element (e.g., gate stack 111 comprising gate electrode 112) in the first dielectric layer
- a second dielectric layer (e.g., dielectric layer 118) over the first dielectric layer
- a bottom via (e.g., bottom portion of connector 122) in the second dielectric layer and in contact with a top surface of the conductive element
- a dielectric spacer (e.g., shielding layer 116) lining a first sidewall (e.g., right sidewall) of the bottom via, wherein the dielectric spacer is in contact with a top surface of the first dielectric layer (e.g., 108)
Regarding Claim 9, Chang (see, e.g., Fig. 2) shows that the dielectric spacer (e.g., 116) is in contact with the second dielectric layer (e.g., 118).
Regarding Claim 10, Chang (see, e.g., Fig. 2) shows a top via (e.g., top portion of connector 122) over and electrically connected with the bottom via, wherein the top via is wider than the bottom via.
Regarding Claim 13, Chang (see, e.g., Fig. 2) shows that the second dielectric layer (e.g., 118) has a portion vertically overlaps the conductive element (e.g., 111).
Regarding Claim 14, Chang (see, e.g., Fig. 2) shows that a second sidewall (e.g., left sidewall) of the bottom via is in contact with the second dielectric layer (e.g., 118), and the first sidewall of the bottom via is spaced apart from the second dielectric layer through the dielectric spacer (e.g., 116), the second sidewall being opposite to the first sidewall.
Regarding Claim 16, Chang (see, e.g., Fig. 2) shows all aspects of the instant invention, including an interconnect structure, comprising:
- a first dielectric layer (e.g., dielectric layer 108)
- a conductive element (e.g., gate stack 111 comprising gate electrode 112) in the first dielectric layer
- a second dielectric layer (e.g., dielectric layer 118) over the first dielectric layer
- a bottom via (e.g., bottom portion of connector 122) in the second dielectric layer and in contact with a top surface of the conductive element
- a dielectric spacer (e.g., shielding layer 116 or spacer 104) lining a sidewall (e.g., right sidewall) of the bottom via, wherein a bottom surface of the dielectric spacer is lower than a top surface of the first dielectric layer (e.g., 108)
Regarding Claim 17, Chang (see, e.g., Fig. 2) shows an etch stop layer (e.g., shielding layer 116) between the first dielectric layer (e.g., 108) and the second dielectric layer (e.g., 118), wherein the bottom surface of the dielectric spacer (e.g., spacer 104) is lower than a bottom surface of the etch stop layer.
Regarding Claim 18, Chang (see, e.g., Fig. 2) shows that a first portion of the etch stop layer (e.g., portion of 116 proximate to A1) is in contact with the dielectric spacer (e.g., 104), and a second portion of the etch stop layer (e.g., portion of 116 proximate to A2) is in contact with the bottom via (e.g., bottom portion of 122).
Regarding Claim 19, Chang (see, e.g., Fig. 2) shows that the second portion of the etch stop layer (e.g., portion of 116 proximate to A2) extends to the top surface of the conductive element (e.g., 111).
Regarding Claim 20, Chang (see, e.g., Fig. 2) shows that the sidewall of the bottom via is spaced apart from the second dielectric layer (e.g., 118) through the dielectric spacer (e.g., 116 or 104).
Regarding Claim 21, Chang (see, e.g., Fig. 2) shows that the bottom surface of the dielectric spacer (e.g., spacer 104) is lower than a top surface of the conductive element (e.g., 111).
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US2007/0224824).
Regarding Claim 1, Chen (see, e.g., Fig. 11) shows all aspects of the instant invention, including an interconnect structure, comprising:
- a first dielectric layer (e.g., ULK ILD layer 10)
- a conductive element (e.g., interconnect structure comprising metal filler 13 and barrier metal film 12) in the first dielectric layer
- a second dielectric layer (e.g., ULK ILD layer 40) over the first dielectric layer
- a bottom via (e.g., bottom portion of interconnect structure 150 in via regions 52/53, and comprising barrier metal film 48 and metal fill 49) in the second dielectric layer and in contact with a top surface of the conductive element, wherein a first sidewall of the bottom via (e.g., inner sidewall) is in contact with the second dielectric layer
- a dielectric spacer (e.g., carbon-rich area 146 of ULK material 41) lining a second sidewall of the bottom via (e.g., outer sidewall) opposite to the first sidewall of the bottom via, wherein the second sidewall of the bottom via is spaced apart from the second dielectric layer through the dielectric spacer.
Regarding Claim 6, Chen (see, e.g., Fig. 11) shows an etch stop layer (e.g., cap layer 42) between the first dielectric layer (e.g., 10) and the second dielectric layer (e.g., 40), wherein the etch stop layer is in contact with the dielectric spacer (e.g., 146).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 8-9 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8, 15, and 18 of U.S. Patent No. 10,777,452.
Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in the patent, and is a broader statement of the invention for which the patent was granted.
Claim 1 of patent No. 10,777,452 anticipates claim 8 of the instant invention.
Claim 1 of patent No. 10,777,452 anticipates claim 9 of the instant invention.
Claims 1 and 8 of patent No. 10,777,452 anticipates claim 16 of the instant invention.
Claims 15 and 18 of patent No. 10,777,452 anticipates claim 8 of the instant invention.
Claims 15 and 18 of patent No. 10,777,452 anticipates claim 16 of the instant invention.
Allowable Subject Matter
Claims 4-5 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose interconnect structures comprising vias with a dielectric spacer, and having features similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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