Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 06/16/2026. Currently, claims 1-18 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Species I (Figures 1-3), claims 1-18, in the reply filed on 06/16/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brun et al (US 20230074181 A1).
Regarding claim 1, Figure 1 of Brun discloses an assembly structure, comprising:
a substrate (112, [0034]);
a molded structure (108, [0033]) disposed over and electrically connected to the substrate, wherein the molded structure includes at least one semiconductor device (106B, [0032]), at least one inactive element (106A, [0032] and [0034], considering die with passive circuits only) and an encapsulant (in 108, [033]) encapsulating the at least one semiconductor device and the at least one inactive element;
a redistribution structure (layer between 108 and 130) disposed on and electrically connected to the molded structure; and
an upper electronic device (130, [0037], considering dies 102 including the molding is an electronic device on a broadest reasonable interpretation) disposed over and electrically connected to the redistribution structure, wherein the at least one inactive element (106A) is configured to provide a vertical conduction path between the upper electronic device (130) and the substrate (112), and the upper electronic device (130) does not electrically connected to the substrate through (since no via in 106B) the at least one semiconductor device (106B).
Regarding claim 2, Figure 1 of Brun discloses that the assembly structure of claim 1, wherein the upper electronic device (130) is electrically connected to the redistribution structure by hybrid bonding ([0040]).
Regarding claim 3, Figure 1 of Brun discloses that the assembly structure of claim 1, wherein the upper electronic device (130) is electrically connected to the redistribution structure through a plurality of solder materials ([0035] and [0039]).
Regarding claim 4, Figure 1 of Brun discloses that the assembly structure of claim 1, wherein the upper electronic device (130) vertically overlaps the at least one inactive element (106A).
Regarding claim 5, Figure 1 of Brun discloses that the assembly structure of claim 1, wherein a width of the upper electronic device (130) is substantially equal to a width of the molded structure (108).
Regarding claim 6, Figure 1 of Brun discloses that the assembly structure of claim 5, wherein a lateral surface of the upper electronic device (130) is substantially aligned with a lateral surface of the molded structure (108).
Regarding claim 7, Figure 1 of Brun discloses that the assembly structure of claim 1, wherein a function of the upper electronic device (130) is different from a function of the at least one semiconductor device (106B) ([0029]-[0030]).
Regarding claim 8, Figure 1 of Brun discloses that the assembly structure of claim 1, wherein the at least one inactive element (106A) includes a main portion and at least one through via (vertical line of conductive material is passing through 106A based on Figure 1) extending through the main portion, and a second surface (bottom surface) of the encapsulant is substantially coplanar with a second surface (bottom surface in the Figure 1) of the at least one inactive element (106A) and a second surface (bottom surface in Figure 1) of the at least one semiconductor device (106B).
Regarding claim 9, Figure 1 of Brun discloses that the assembly structure of claim 8, further comprises: at least one first bump (connector under 106A) connecting the at least one through via (in 106A) and the substrate (112); and at least one second bump (connector under 106B) connecting the second surface of the at least one semiconductor device (106B) and the substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12 and 16-18 are rejected under 35 U.S.C. 103 as being obvious over Brun et al (US 20230074181 A1).
Regarding claim 10, Figure 1 of Brun does not explicitly teach that the assembly structure of claim 9, wherein the at least one first bump and the at least one second bump are formed concurrently.
However, this above limitation is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art of Brun who teaches the structure as claimed. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Regarding claim 11, Figure 1 of Brun does not explicitly teach that the assembly structure of claim 9, wherein the at least one second bump includes a reflowable material configured to control a gap between the molded structure and the substrate.
However, the above limitation does not distinguish the present invention over the prior art of Brun who teaches the structure which is capable of performing the intended use as claimed. Moreover, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ 2d 1647 (1987).
Regarding claim 12, Figure 1 of Brun discloses that the assembly structure of claim 9, wherein the at least one first bump (connectors under 106A) includes a plurality of first bumps, the at least one second bump (connectors under 106B) includes a plurality of second bumps.
Brun does not explicitly teach that a first gap between adjacent two of the plurality of first bumps is less than a second gap between adjacent two of the plurality of second bumps.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to form a device with improved performance and lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 16, Figure 1 of Brun discloses that the assembly structure of claim 1, wherein the at least one semiconductor device (106B, [0030]-[0031]) includes a main portion and an active circuit structure disposed on the main portion, wherein the at least one inactive element (106A) includes a main portion and at least one through via extending through the main portion.
Brun does not explicitly teach that wherein a thickness of the main portion of the at least one semiconductor device is less than a thickness of the main portion of the at least one inactive element.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to form a device with improved performance and lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 17, Figure 1 of Brun discloses that the assembly structure of claim 16, wherein a material of the main portion of the at least one semiconductor device (106B) is same as a material of the main portion of the at least one inactive element (106A).
Regarding claim 18, Figure 1 of Brun discloses that the assembly structure of claim 16, wherein a first surface of the at least one through via of the at least one inactive element (106A) is exposed from a first surface (top surface in the Figure 1) of the at least one inactive element, and a second surface (bottom surface in Figure 1) of the at least one through via of the at least one inactive element is exposed from a second surface of the at least one inactive element.
Claim 13 is rejected under 35 U.S.C. 103 as being obvious over Brun et al (US 20230074181 A1) in view of Kim et al (US 20190280374 A1).
Regarding claim 13, Figure 1 of Brun discloses that the assembly structure of claim 1, wherein the redistribution structure (layer between 108 and 130) includes a plurality of dielectric layers (multiple layers based on Figure 1), a plurality of circuit layers covered by the plurality of dielectric layers and a plurality of inner vias connecting adjacent two of the plurality of circuit layers.
Brun does not teach that wherein the plurality of inner vias taper toward the molded structure.
However, KIM is a pertinent art which teaches a semiconductor device package wherein a semiconductor device (300a) is encapsulated in molding layer (355c), wherein redistribution structures are formed on both side of the semiconductor device having inner via in the redistribution structures that taper toward the molding structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the vias with taper toward the molded structure instead of taper not toward the molded structure in the device of Brun according to the teaching of KIM, since the court has held that a simple substitution of one known element for another (tapering the vias towards the molding structure instead of not toward the molding structure) to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007). (please see Smith v. Hayashi, 209 USPQ 754 (Bd. of Pat. Inter. 1980)).
Claims 14-15 are rejected under 35 U.S.C. 103 as being obvious over Brun et al (US 20230074181 A1) in view of Wu et al (US 20210098421 A1).
Regarding claims 14-15, Figure 1 of Brun does not teach that the assembly structure of claim 1, wherein the at least one semiconductor device includes a first semiconductor device and a second semiconductor device disposed side by side, and the at least one inactive element includes a first inactive element and a second inactive element disposed around the first semiconductor device and the second semiconductor device, wherein a size of the first inactive element is different from and a size of the second inactive element from a top view. Or
Figure 1 of Brun does not teach assembly structure of claim 1, wherein a width of the at least one semiconductor device is greater than a width of the at least one inactive element.
However, Wu is a pertinent art which teaches a package component for carrying a device package and an insulating layer thereon includes a molding layer, first and second redistribution structures disposed on two opposite sides of the molding layer, a semiconductor die, and a through interlayer via (TIV). A hardness of the molding layer is greater than that of the insulating layer that covers the device package. The device package is mounted on the second redistribution structure, and the insulating layer is disposed on the second redistribution structure opposite to the molding layer. The semiconductor die is embedded in the molding layer and electrically coupled to the device package through the second redistribution structure. The TIV penetrates through the molding layer to connect the first and the second redistribution structure. Figures 1-12 of Wu teach such a package wherein plurality of active and inactive devices with different sizes are molded and connected to upper and lower packages in the method of forming a semiconductor device due to continuous improvements in the integration density of a variety of integrated circuit components (e.g., transistors, diodes, resistors, capacitors, etc.). In the packaging of integrated circuit components, semiconductor dies are stacked and bonded to other package components such as interposers and package substrates. As the demand for miniaturization, the increased density and corresponding decrease in area occupied by the integrated circuit components has surpassed the ability to bond the semiconductor die onto the package component ([0002]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the assembly structure of Brun as claimed above according to the teaching of Wu in order to form a package with higher integration density of a variety of integrated circuit components ([0002] of Wu).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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