Prosecution Insights
Last updated: October 23, 2026
Application No. 18/630,191

SEMICONDUCTOR DEVICE WITH NECK LAYER AND METHOD FOR FABRICATING THE SAME

Non-Final OA §102
Filed
Apr 09, 2024
Priority
Mar 15, 2024 — divisional of 18/606,384
Examiner
WARREN, MATTHEW E
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
895 granted / 1020 resolved
+19.7% vs TC avg
Minimal +5% lift
Without
With
+5.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
15 currently pending
Career history
1038
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
52.1%
+12.1% vs TC avg
§102
35.3%
-4.7% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1020 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 1 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son et al. (US Pub. 2018/0342521 A1). In re claim 1, Son et al. shows (fig. 1B) a semiconductor device, comprising: a substrate (100); at least two bit line structures (BL @304a and 304b) positioned on the substrate, spaced apart from each other, and respectively comprises: a bit line top conductive layer (304) positioned on the substrate; and a bit line capping layer (314) positioned on the bit line top conductive layer; a plurality of inner spacer layers (404) conformally positioned on sides of the at least two bit line structures; a plurality of outer spacer layers (417) conformally positioned on the plurality of inner spacer layers; a contact layer (BC, 414) positioned on the substrate and between the at least two bit line structures; and a conductive neck layer (418b) positioned on the contact layer and between the at least two bit line structures; wherein a width of a top surface of the bit line capping layer is less than a width of a bottom surface of the bit line capping layer (because the capping layer has a component 126 that cuts into the top surface). Allowable Subject Matter Claims objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hummler (US 6,734,059 B1), Lee (US Pub. 2022/0115382), and Son (CN-108933135-A) also disclose various elements of the claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KRETELIA GRAHAM can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Apr 09, 2024
Application Filed
Sep 28, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772457
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
3y 3m to grant Granted Oct 20, 2026
Patent 12762388
Ferroelectric Memory Device And Electronic Device Including The Same
3y 11m to grant Granted Oct 13, 2026
Patent 12764967
BACK-END ACTIVE DEVICE AND LOGIC GATE
2y 7m to grant Granted Oct 13, 2026
Patent 12757374
MEMORY DEVICE INCLUDING CAPACITOR CONTACTS HAVING DIFFERENT MATERIALS AND METHOD FOR PREPARING THE SAME
2y 8m to grant Granted Oct 06, 2026
Patent 12751025
INSULATING-GATE BIPOLAR TRANSISTORS INCLUDING A REVERSE CONDUCTING DIODE
3y 1m to grant Granted Sep 29, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+5.0%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1020 resolved cases by this examiner. Grant probability derived from career allowance rate.

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