DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kato et al. (U.S. Publication No. 2014/03683149).
Regarding claim 1, Kato teaches a semiconductor device, comprising:
a plurality of semiconductor dies (Fig. 1, dies 100-400), arranged in a stacked structure (Fig. 1),
wherein each semiconductor die comprises an identifier generation circuit (Fig. 2) electrically connected to the identifier generation circuits of other semiconductor dies (Fig. 2),
wherein in response to a first semiconductor die (200-400) not being a bottom semiconductor die within the stacked structure (Fig. 1-2), a first identifier generation circuit of the first semiconductor die is configured to automatically generate a first chip identifier for the first semiconductor die based on an input signal generated by a second identifier generation circuit of a second semiconductor die neighboring to and below the first semiconductor die (see paragraph [0043]-[0046]).
Regarding claim 2, Kato teaches the semiconductor device of Claim 1, wherein the stacked structure is a three-dimensional stacked structure (Fig. 1).
Regarding claim 3, Kato teaches the semiconductor device of Claim 1, wherein in response to the second semiconductor die being the bottom semiconductor die within the stacked structure, the second identifier generation circuit of the second semiconductor die is configured to automatically generate a second chip identifier for the second semiconductor die using a preset value (see paragraphs [0036]-[0041], the bottom chip receives an input of a reference voltage from the interposer, and therefore knows it is the bottom chip and sets accordingly to a predetermined value such as 0 or 1).
Regarding claim 4, Kato teaches the semiconductor device of Claim 3, wherein the input signal of the first identifier generation circuit of the first semiconductor die is the second chip identifier generated by the second identifier generation circuit (see paragraphs [0043]-[0046]).
Regarding claim 19, Kato teaches the semiconductor device of Claim 4, wherein the first identifier generation circuit is electrically connected to the second identifier generation circuit through a plurality of through-silicon vias within the second semiconductor die (Kato claim 13).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kato in view of Imai (U.S. Publication No. 2012/0025391)
Regarding claim 5, Kato teaches the semiconductor device of Claim 4, wherein the first chip identifier generated by the first identifier generation circuit is a bit-shifted value of the second chip identifier (Kato paragraph [0041], the first identifier is a bit-increased value of the second identifier).
Kato does not specifically teach that it is a bit-shifted value. However, Imai teaches that a bit shift register can be used to increase the value of a chip identifier in a stack (see Imai paragraph {0054]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the bit increase of Kato could have been accomplished through a bit shift because it would have been a simple substitution of one known method of increasing a value for another with predictable results.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kato in view of Hamada (U.S. Publication No. 2017/0110159).
Regarding claim 6, Kato teaches the semiconductor device of Claim 4, but does not specifically wherein the first chip identifier and the second chip identifier are different one-hot codes.
However, Hamada teaches that one-hot encoding can be used for chip identifiers (Hamada paragraph [0091]). It would have been obvious to a person of skill in the art at the time of the effective filing date that one-hot encoding could have been used as the identifier because it would have been a simple substitution one numbering system for another with predictable results.
Allowable Subject Matter
Claims 7-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 7-13, the prior art, alone or in combination, fails to teach or suggest wherein each first buffer circuit receives a corresponding bit of the second chip identifier from the corresponding first input port.
Regarding claims 14-18, the prior art, alone or in combination, fails to teach or suggest the plurality of second input ports of the second identifier generation circuit of the second semiconductor die are floating.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EVAN G CLINTON/Primary Examiner, Art Unit 2899
Prosecution Insights