DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: it appears the reference number “116” in paragraph [0043] was meant to be “118”.
Appropriate correction is required.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 1: it appears that “the reference current” in line(s) 5 was meant to be -- a reference current --.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Antonyan (US 2019/0348118).
Regarding claim 1, Antonyan discloses a current reference circuit for a memory cell (fig. 6, 9), comprising:
a configurable resistor network (420; fig. 9), wherein the configurable resistor network is configured to emulate a resistive element (a variable resistance element MTJ; fig. 2) of the memory cell (“a resistance of the emulation resistor REMU is the same as one of the MTJ elements MTJ” para 0069);
a step current generator circuit (410, 430, 440; fig. 9 para 0067) connected to the configurable resistor network (420), wherein the step current generator circuit is used to adjust (equation 3; para 0060) the reference current level (Iref; fig. 6) provided by the current reference circuit and includes:
a current generator circuit (430; fig. 9); and
a current mirror circuit (440; fig. 9) connected to the current generator circuit (430); and
wherein the configurable resistor network (420), and the step current generator circuit (410, 430, 440) are configured to track process, voltage and temperature (PVT) variations (fig. 7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Antonyan (US 2019/0348118).
The disclosure of fig(s). 1-10 of Antonyan is incorporated into an embodiment as considered below, since elements are analogous and similarly referenced (i.e. compensation circuit and emulation resistor network). Therefore, before the effective filing date of the invention, it would have been obvious to one with ordinary skill in the art to modify the figure(s) with the embodiment as taught for the purpose of improving the overall performance by compensating for leakage current, which is common and well known in the art to improve the overall integrity of data storage (para 0003-0006).
Regarding claim 2, Antonyan discloses, in an embodiment, the current reference circuit of claim 1, further comprising: a replica access path (P3; fig. 17), wherein the replica access path is connected to a first terminal (N3; fig. 17) of the configurable resistor network (420; fig. 17, as detailed in fig. 9) and a replica selector circuit (P4; fig. 17) connected to a second terminal (N4; fig. 17) of the configurable resistor network (420).
Regarding claim 3, Antonyan discloses, in the embodiment, the current reference circuit of claim 2, wherein the replica access path emulates (i.e. emulates IREAD; fig. 17) an access path (P1; fig. 17) associated with the memory cell and the replica selector circuit (P4) emulates (i.e. emulates ILEAK; fig. 17) a selector circuit (P2; fig. 17) associated with the memory cell.
Regarding claim 4, Antonyan discloses, in the embodiment, the current reference circuit of claim 2, wherein the replica access path includes one or more transistor devices that match the resistance of logic devices, metal wire resistance and leakage associated with the memory cell (i.e. via an emulation resistor RMTJ; fig. 17, further para 0069).
Regarding claim 10, Antonyan discloses, in the embodiment, the current reference circuit of claim 2, wherein the replica selector circuit is an array of transistor devices wherein the array includes one of: four transistor devices or nine transistor devices (N3, N4, P3, P4; fig. 17).
Regarding claim 11, Antonyan discloses, in the embodiment, the current reference circuit of claim 10, wherein the four transistor devices include two sets of two transistors (N3, N4, P3, P4; fig. 17), wherein the two transistors from each set of two transistors are connected in a parallel configuration (P3, P4 and/or N3, N4) and the two sets of two transistors are connected in a series configuration (P3, N3 and/or P4, N4).
Regarding claim 12, Antonyan discloses, in the embodiment, the current reference circuit of claim 3, wherein the replica selector circuit is a single transistor device that tracks (i.e. via monitor BL and cells of array 120c; fig. 17) the selector circuit associated with the memory cell.
Antonyan does not expressly disclose NMOS.
Antonyan teaches NMOS and PMOS type transistors. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device is modifiable as taught because it is common and well known in the art that n-type and p-type are obvious variants that is used interchangeably for a memory transistor, and further considered to be directed to the same subject matter.
Regarding claim 13, Antonyan discloses, in the embodiment, the current reference circuit of claim 1, the step current generator circuit further includes: a first terminal of a switch device (P3; fig. 17) connected to the current mirror circuit (P4, P5, N1, N2; fig. 17) and a second terminal (N3; fig. 17) of the switch device connected to the configurable resistor network, wherein: upon enabling (i.e. via VREAD _BIAS; fig. 17) the switch device, a current (ILEAK; fig. 17) generated by the current generator circuit and mirrored by the current mirror circuit is used to adjust (i.e. via IREAD-ILEAK; fig. 17) the reference current level provided by the current reference circuit.
Regarding claim 14, Antonyan discloses, in the embodiment, the current reference circuit of claim 1, wherein the low resistance state (LRS) is used to represent a logic value of 0 and the high resistance state (HRS) is used to represent a logic value of 1 (claim 7).
Claim(s) 5-6, 8, 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Antonyan (US 2019/0348118) in view of Schwartz et al. (US 2017/0084343 “Schwartz”).
The disclosure of fig(s). 1-10 of Antonyan is incorporated into an embodiment as considered below, since elements are analogous and similarly referenced (i.e. compensation circuit and emulation resistor network). Therefore, before the effective filing date of the invention, it would have been obvious to one with ordinary skill in the art to modify the figure(s) with the embodiment as taught for the purpose of improving the overall performance by compensating for leakage current, which is common and well known in the art to improve the overall integrity of data storage (para 0003-0006).
Regarding claim 5, Antonyan discloses, in the embodiment, the current reference circuit of claim 2, wherein the configurable resistor network includes: a first terminal of a first resistor device connected to the replica access path, connected to the replica selector circuit (fig. 17).
Antonyan does not expressly disclose a second terminal of the first resistor connected to a first terminal of a second resistor device; a second terminal of the second resistor device connected to a first terminal of a third resistor device; a second terminal of the third resistor device connected to a first terminal of a step resistor device; a second terminal of the step resistor device.
Schwartz discloses a second terminal of the first resistor connected to a first terminal of a second resistor device; a second terminal of the second resistor device connected to a first terminal of a third resistor device; a second terminal of the third resistor device connected to a first terminal of a step resistor device; a second terminal of the step resistor device (fig. 4, 5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Antonyan is modifiable as taught by Schwartz for the purpose of tracking bit cell current, in turn facilitating data accessing schemes by reducing current consumption and overall surface area allocation to achieve a more space-efficient flash memory architecture (para 0014 of Schwartz).
Regarding claim 6, Antonyan discloses the current reference circuit of claim 5, provides a high resistance (RH) that matches a high resistance state (HRS) (claim 7).
Antonyan does not expressly disclose verify level.
Schwartz discloses verify level (i.e. program-verify level; para 0027).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Antonyan is modifiable as taught by Schwartz for the purpose of tracking bit cell current, in turn facilitating data accessing schemes by reducing current consumption and overall surface area allocation to achieve a more space-efficient flash memory architecture (para 0014 of Schwartz).
Regarding claim 8, Antonyan discloses, in the embodiment, the current reference circuit of claim 2, wherein the configurable resistor network includes: a first terminal of a first resistor device connected to the replica access path; device connected to the replica access path; connected to the replica access path; connected to the replica selector circuit (fig. 17).
Antonyan does not expressly disclose a second terminal of the first resistor device connected to a first terminal of a first switch device; a first terminal of a second resistor; a second terminal of the second resistor device connected to a first terminal of a second switch device; a first terminal of a third resistor network; a second terminal of the third resistor device connected to a first terminal of a third switch device; the second terminals of the first switch device, the second switch device and the third switch device connected to the first terminal of a step resistor device; and a second terminal of the step resistor device.
Schwartz discloses a second terminal of the first resistor device connected to a first terminal of a first switch device; a first terminal of a second resistor; a second terminal of the second resistor device connected to a first terminal of a second switch device; a first terminal of a third resistor network; a second terminal of the third resistor device connected to a first terminal of a third switch device; the second terminals of the first switch device, the second switch device and the third switch device connected to the first terminal of a step resistor device; and a second terminal of the step resistor device (fig. 4, 5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Antonyan is modifiable as taught by Schwartz for the purpose of tracking bit cell current, in turn facilitating data accessing schemes by reducing current consumption and overall surface area allocation to achieve a more space-efficient flash memory architecture (para 0014 of Schwartz).
Regarding claim 15, Antonyan discloses a system comprising:
a memory device (10c; fig. 17) wherein the memory device includes a memory cell (110c; fig. 17);
a first terminal of an access path (P1; fig. 17) connected (via a SEL switch; fig. 17) to a first terminal of the memory cell (SL terminal of the memory cell; fig. 17); and
a current reference circuit (400c; fig. 17), wherein the current reference circuit includes:
a configurable resistor network (420; fig. 17), wherein the configurable resistor network is configured to emulate (i.e. via an emulation resistor RMTJ; fig. 17) a resistive element of the memory cell (MTJ; fig. 17);
a step current generator circuit (N1-N4, P3-P5; fig. 17) connected to the configurable resistor network (420), wherein the step current generator circuit is used to adjust (i.e. via equation IREAD-ILEAK; fig. 17) a reference current level (a current equal to IREAD-ILEAK, i.e. reference current level = IREAD-ILEAK) provided by the current reference circuit (400c); and
a replica access path (P3; fig. 17), wherein a first terminal of the replica access path is connected to a first terminal (N3) of the configurable resistor network (420) and wherein the replica access path emulates (i.e. emulating an IREAD; fig. 17) the access path (P1) associated with the memory cell (replica access path P3 emulates the access path P1 by the current IREAD); and
a sense amplifier circuit (320a; fig. 17) connected to the access path (i.e. via the SEL switch) and the replica access path (i.e. via a READ switch; fig. 17), wherein the sense amplifier circuit (320A) is configured to sense variations (i.e. in a read operation; para 0099) between the memory device (at VIN; fig. 17) and level provided by the current reference circuit (at VREF; fig. 17) to determine a data value stored in the memory cell (to determine a value stored in the selected memory cell; para 0099).
Antonyan does not expressly disclose sense variations in current and the reference current level.
Schwartz discloses sense (i.e. via sense amplifier 110; fig. 1) variations in current (IBIT; fig. 1) and the reference current level (IREF; fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Antonyan is modifiable as taught by Schwartz for the purpose of tracking bit cell current, in turn facilitating data accessing schemes by reducing current consumption and overall surface area allocation to achieve a more space-efficient flash memory architecture (para 0014 of Schwartz).
Regarding claim 16, Antonyan discloses the system of claim 15 further comprising: a selector circuit (P2; fig. 17); and the current reference circuit further comprising: a replica selector circuit (P4; fig. 17) connected to a second terminal (N4; fig. 17) of the configurable resistor network and wherein the replica selector circuit (P4) emulates (i.e. emulates ILEAK; fig. 17) a selector circuit (P2) associated with the memory cell.
Antonyan does not expressly disclose connected (a SEL switch; fig. 17) to a second terminal of the memory cell (BL terminal; fig. 17).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Antonyan is modifiable as taught for the purpose of facilitating data accessing schemes by improving the overall performance by compensating for leakage current, which is common and well known in the art to improve the overall integrity of data storage (para 0003-0006).
Regarding claim 17, Antonyan discloses the current reference circuit from the system of claim 15 wherein the step current generator circuit includes: a current generator circuit (P4, P5; fig. 17); and a current mirror circuit (N2, N1; fig. 17) connected to the current generator circuit.
Regarding claim 18, Antonyan discloses the system of claim 15, wherein the sense amplifier circuit includes two input terminals, wherein a second terminal of the access path is connected to one input terminal (VIN; fig. 17) of the sense amplifier circuit and a second terminal of the replica access path is connected to another input terminal (VREF; fig. 17) of the sense amplifier circuit.
Regarding claim 19, Antonyan discloses the system of claim 16, wherein the configurable resistor network includes: a first terminal of a first resistor device connected to the replica access path; connected to the replica access path; connected to the replica access path; connected to the replica selector circuit.
Antonyan does not expressly disclose a second terminal of the first resistor device connected to a first terminal of a first switch device; a first terminal of a second resistor device; a second terminal of the second resistor device connected to a first terminal of a second switch device; a first terminal of a third resistor network; a second terminal of the third resistor device connected to a first terminal of a third switch device; the second terminals of the first switch device, the second switch device and the third switch device connected to the first terminal of a step resistor device; and a second terminal of the step resistor device.
Schwartz discloses a second terminal of the first resistor device connected to a first terminal of a first switch device; a first terminal of a second resistor device; a second terminal of the second resistor device connected to a first terminal of a second switch device; a first terminal of a third resistor network; a second terminal of the third resistor device connected to a first terminal of a third switch device; the second terminals of the first switch device, the second switch device and the third switch device connected to the first terminal of a step resistor device; and a second terminal of the step resistor device (fig. 4, 5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Antonyan is modifiable as taught by Schwartz for the purpose of tracking bit cell current, in turn facilitating data accessing schemes by reducing current consumption and overall surface area allocation to achieve a more space-efficient flash memory architecture (para 0014 of Schwartz).
Regarding claim 20, Antonyan discloses a system comprising:
a memory device (10c; fig. 17) wherein the memory device includes a memory cell (110c; fig. 17);
a current reference circuit (400c; fig. 17), wherein the current reference circuit includes:
a configurable resistor network (420; fig. 17), wherein the configurable resistor network is configured to emulate (i.e. via an emulation resistor RMTJ; fig. 17) a resistive element of the memory cell (MTJ; fig. 17);
a step current generator circuit (N1-N4, P3-P5; fig. 17) connected to the configurable resistor network (420), wherein the step current generator circuit is used to adjust (i.e. via equation IREAD-ILEAK; fig. 17) a reference current level (a current equal to IREAD-ILEAK, i.e. reference current level = IREAD-ILEAK) provided by the current reference circuit (400c); and
a sense amplifier circuit (320a; fig. 17) configured to sense variations (i.e. in a read operation; para 0099) between the memory device (at VIN; fig. 17) and level provided by the current reference circuit (at VREF; fig. 17) to determine a data value stored in the memory cell (to determine a value stored in the selected memory cell; para 0099).
Antonyan does not expressly disclose sense variations in current and the reference current level.
Schwartz discloses sense (i.e. via sense amplifier 110; fig. 1) variations in current (IBIT; fig. 1) and the reference current level (IREF; fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Antonyan is modifiable as taught by Schwartz for the purpose of tracking bit cell current, in turn facilitating data accessing schemes by reducing current consumption and overall surface area allocation to achieve a more space-efficient flash memory architecture (para 0014 of Schwartz).
Allowable Subject Matter
Claim(s) 7, 9 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 7, the prior art fails to teach or suggest the claimed limitations, namely switching the first terminal of the third resistor device to connect directly to the replica access path provides a low resistance (RL) that matches a low resistance state (LRS) verify level; switching the first terminal of the second resistor device to connect directly to the replica access path provides a middle resistance that matches the normal resistance state; and adjusting the step resistor device provides additional adjustment to a resistance value provided by the configurable resistor network.
With respect to dependent claim 9, the prior art fails to teach or suggest the claimed limitations, namely disabling the second switch device and the third switch device provides a high resistance (RH) that matches the high resistance state (HRS) verify level; disabling the first switch device and the third switch device provides a middle resistance that matches the normal resistance state; disabling the first switch device and the second switch device provides a low resistance (RL) that matches the low resistance state (LRS) verify level; and adjusting the step resistor device provides additional adjustment to a resistance value provided by the configurable resistor network..
The allowable claims are supported in at least fig. 2 of the instant application.
Conclusion
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/UYEN SMET/
[AltContent: connector] Primary Examiner, Art Unit 2824
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