DETAILED ACTION
The RCE filed March 26, 2026 has been entered. Claims 1-20 are pending. Claims 1, 11 and 18 are independent.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-14 and 18-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Vikash et al. (US 2013/0322190).
Regarding independent claims 11 and its method claim 18, Vikash et al. teach a memory circuit (FIG. 2), comprising:
a memory array (102) comprising a plurality of first memory cells (MEMORY ARRAY);
a tracking column (202) comprising one or more second memory cells (DMY BITCELL), wherein each of the one or more second memory cells is coupled to a first tracking bit line (DMYBL), a second tracking bit line (DMYBLB), and a first tracking word line (DMYWL), and configured to mimic a write operation performed on the first memory cells, wherein each of the one or more second memory cells stored a fixed logic value1, and wherein a first signal present on the first tracking bit line and a second signal present on the second tracking bit line have been provided at a first logic state and a second logic state (FIG. 4: DMYBL/DMYBLB, and accompanying disclosure), respectively, prior to the write operation (e.g., para. 0008: … the write cycle time of the actual memory cells is tracked by writing a data bit at … to a dummy memory cell …, i.e., tracking dummy write operation performing prior to actual memory write operation); and
a controller (150) operatively coupled to the memory array and the tracking column, and configured to adjust a timing of a falling edge of an internal clock signal according to a rising edge of the second signal present on the second tracking bit line (see the EXMINER’S MARKUP below, i.e., claimed second signal though claimed internal clock signal, 1->2->3->4).
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Vikash et al. are silent with respect to a first and a second tracking bit lines are extending entirely along the memory array.
However, extending the tracking bit lines from Vikash’s partial-tracking bit lines to full- tracking bit lines is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Rimondi et al. (US 2013/0128656), FIGS. 1 or 4, DBLT and DBLC, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Rimondi et al. to the teaching of Vikash et al. such that a memory, as taught by Vikash et al., utilizes a tracking bit line, as taught by Rimondi et al., for the purpose of tracking full range of bit lines, further these conventional technology are well established in the art of the memory devices.
Further, regarding method claim 18, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Examiner has an authority to shift the burden to applicant and require applicant to either: (1) show the prior art memory device and the claimed memory device are not substantially identical; or (2) prove, by evidence, that the prior art memory device is not capable of performing the functions claimed. see MPEP 2112.01(I).
Regarding claim 12, Vikash et al. teach the limitations of claim 11.
Vikash et al. further teach the controller is further configured to provide a trigger signal (MUX_OUT) substantially following the second signal (FIG. 4).
Regarding claim 13, Vikash et al. teach the limitations of claim 12.
Vikash et al. further teach a rising edge of the trigger signal determines the timing of the falling edge of the internal clock signal (FIG. 4).
Regarding claim 14, Vikash et al. teach the limitations of claim 11.
Vikash et al. further teach the controller is further configured to pull up a third signal (FIG. 2: DMYWL) present on the first tracking word line coupled to each of the one or more second memory cells, upon identifying a falling edge of the first signal (FIG. 2).
Regarding claim 19, Vikash et al. teach the limitations of claim 11.
Vikash et al. further teach generating a trigger signal substantially follows the second signal, wherein a rising edge of the trigger signal causes the negation of the internal clock signal (FIG. 4).
Regarding claim 20, Vikash et al. teach the limitations of claim 18.
Vikash et al.’ precharge phase (see e.g., para. 0002) do not explicitly disclose prior to the write operation, the first signal has been pre-charged (e.g., para. 0002: precharge phase) to a first logic state and the second signal has been pre-discharged to a second logic state.
However, precharge phase of memory circuit is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize pre-charging prior to read/write memory operations because these conventional technology are well established in the art of the memory devices.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-16 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Vikash et al. (US 2013/0322190) in view of Zhao et al. (US 10,950,298).
Regarding claim 15, Vikash et al. teach the limitations of claim 11.
Vikash et al. are silent with respect to the tracking column further includes one or more third memory cells, wherein each of the one or more third memory cells is coupled to the first tracking bit line, but not coupled to the second tracking bit line or the first tracking word line.
Zhao et al. teach the deficiencies in e.g., FIG. 5 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Zhao et al. to the teaching of Vikash et al. such that a memory, as taught by Vikash et al., utilizes a transistor, as taught by Zhao et al., for the purpose of providing different location of dummy cells, thereby covers a wide range of operating environments.
Regarding claim 16, Vikash et al. teach the limitations of claim 11.
Vikash et al. are silent with respect to the tracking column further includes one or more fourth memory cells, wherein each of the one or more fourth memory cells is coupled to the first tracking bit line and a second tracking word line, but not coupled to the second tracking bit line or the first tracking word line.
Zhao et al. teach the deficiencies in e.g., FIG. 5 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Zhao et al. to the teaching of Vikash et al. such that a memory, as taught by Vikash et al., utilizes a transistor, as taught by Zhao et al., for the purpose of providing different location of dummy cells, thereby covers a wide range of operating environments.
Allowable Subject Matter
Claims 1-10 are allowed.
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s RCE filed 03/26/2026, with respect to the rejection(s) of claims 1-20 under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection. Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 The claimed second memory cells are dummy cells used for tracking purposes. The values stored in these dummy cells are fixed values, which are an inherent characteristic of a memory device. See for example, Rimondi et al. (US 2013/0128656), paragraph [0015]: … the dummy read cell 20 stores a fixed logic value …
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