Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 8/7/2026 is acknowledged.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/27/2025 and 11/11/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
MPEP 2173.03 Correspondence Between Specification and Claims: “A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty.”
Regarding claim 8, the claim is clear on its face, by describing a “coupled” configuration (lines 5-6). However, a conflict exists between the configuration of the claim “a fourth source/drain structure corresponding to the second transistor, and coupled to the second gate portion” and Figs. 3A-3B of the specification because: 1) the figures only illustrate capacitive coupling for the claimed structures “a fourth source/drain structure (AA18) corresponding to the second transistor (TP32), and [capacitively] coupled to the second gate portion (GP33)”; and 2) [0066] and [0071] of the specification only describe “coupled” as conductively coupled. Thus, the scope of the claim is uncertain: 1) whether “coupled” includes capacitive and conductive coupling; or 2) whether “coupled” only includes conductive coupling, and is directed to “the first gate portion (GP34)”; and is therefore indefinite. For the sake of compact prosecution (MPEP 2173.06), claim 8 is interpreted in the instant Office action as follows: “a fourth source/drain structure corresponding to the second transistor, and coupled to the second gate portion” in lines 5-6 is believed to be a typographical error and should be “a fourth source/drain structure corresponding to the second transistor, and coupled to the first gate portion”. However, no changes have been made to the claim language in the instant Office action and the claim is examined as written in accord with MPEP 2111. This interpretation is to be confirmed by applicant in the next office action.
Regarding claim 28, the claim is clear on its face, by describing a “coupled” configuration (lines 5-6). However, a conflict exists between the configuration of the claim “forming a fourth source/drain structure corresponding to the second transistor, and coupled to the second gate portion” and Figs. 3A-3B of the specification because: 1) the figures only illustrate capacitive coupling for the claimed structures “forming a fourth source/drain structure (AA18) corresponding to the second transistor (TP32), and [capacitively] coupled to the second gate portion (GP33)”; and 2) [0066] and [0071] of the specification only describe “coupled” as conductively coupled. Thus, the scope of the claim is uncertain: 1) whether “coupled” includes capacitive and conductive coupling; or 2) whether “coupled” only includes conductive coupling, and is directed to “the first gate portion (GP34)”; and is therefore indefinite. For the sake of compact prosecution (MPEP 2173.06), claim 8 is interpreted in the instant Office action as follows: “forming a fourth source/drain structure corresponding to the second transistor, and coupled to the second gate portion” in lines 5-6 is believed to be a typographical error and should be “forming a fourth source/drain structure corresponding to the second transistor, and coupled to the first gate portion”. However, no changes have been made to the claim language in the instant Office action and the claim is examined as written in accord with MPEP 2111. This interpretation is to be confirmed by applicant in the next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-9, 21-22, and 25-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu (US 20200074039 A1).
Regarding claim 1, Lu discloses a semiconductor device (Fig. 4A), comprising:
a function circuit (210B) configured to receive a first reference voltage signal (NET1/NET2. Note: Fig. 4A shows these signal annotations inverted from the specification [0056]: “correspondingly connected to some signal voltages”) and a second reference voltage signal (VSS; [0049]: “lower supply voltage”; [0032]: “the third power domain”);
an antenna circuit (140) configured to receive the first reference voltage signal (140 as cited includes the entire circuitry, and thus is including all voltages) to share charges with the function circuit (“share charges” either capacitively by the gates of transistors, or conductively through the transistors); and
a first isolation circuit (See annotated figure) disposed between the function circuit and the antenna circuit, and configured to receive the second reference voltage signal (VSS passes through the 1st isolation circuit) to isolate the function circuit and the antenna circuit from each other (transistors T6p/T2p/T4n/T2n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured…to isolate…” circuit 210B from circuit 200).
Illustrated below are marked and annotated figures of Figs. 4A, and 4B of Lu.
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Regarding claim 2, Lu discloses the semiconductor device of claim 1 (Fig. 4B), wherein the first isolation circuit comprises:
a first gate structure (44n) corresponding to a first transistor (T4n) of the first isolation circuit, and configured to receive the first reference voltage signal ([0056]: “T4n…correspondingly connected to…NET2”); and
a first source/drain structure (66n) corresponding to the first transistor, and configured to receive the second reference voltage signal ([0049]: “lower supply voltage VSS”).
Regarding claim 5, Lu discloses the semiconductor device of claim 2 (Fig, 4A), further comprising:
a second isolation circuit (See annotated figure) configured to isolate the antenna circuit (transistors T5p/T3p/T1p/T3n/T1n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured to isolate…” circuit 210A from circuit 200);
a first conductive segment (Fig. 4B: segment 34, See annotated figure) configured to transmit the second reference voltage signal ([0055]: “power rail 34 is conducted with the common lower supply voltage VSS of the first power supply”) to the first isolation circuit; and
a second conductive segment (VG) configured to transmit the second reference voltage signal ([0055]: “power rail 34 is conducted with the common lower supply voltage VSS of the first power supply”) to the second isolation circuit,
wherein the antenna circuit is disposed between (portion 200 is “between” in the X direction) the first conductive segment and the second conductive segment.
Note that claims 1 and 5 were previously addressed above, however, they’re being addressed differently here based on the reading of the reference, particularly to the assignment of the “first reference voltage signal” in order to address the dependent claim 6.
Regarding claim 1, Lu discloses a semiconductor device (Fig. 4A), comprising:
a function circuit (210B) configured to receive a first reference voltage signal (VDD2);
an antenna circuit (140) configured to receive the first reference voltage signal (140 as cited includes the entire circuitry, and thus is including all voltages) to share charges with the function circuit (“share charges” either capacitively by the gates of transistors, or conductively through the transistors); and
a first isolation circuit (See annotated figure) disposed between the function circuit and the antenna circuit, and configured to receive the second reference voltage signal (VSS passes through the 1st isolation circuit) to isolate the function circuit and the antenna circuit from each other (transistors T6p/T2p/T4n/T2n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured…to isolate…” circuit 210B from circuit 200).
Regarding claim 5, Lu discloses the semiconductor device of claim 2 (Fig, 4A), further comprising:
a second isolation circuit (See annotated figure) configured to isolate the antenna circuit (transistors T5p/T3p/T1p/T3n/T1n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured to isolate…” circuit 210A from circuit 200);
a first conductive segment (Fig. 4B: a corresponding segment/portion of 34, See annotated figure) configured to transmit the second reference voltage signal ([0055]: “power rail 34 is conducted with the common lower supply voltage VSS of the first power supply”) to the first isolation circuit; and
a second conductive segment (a corresponding segment/portion of 34) configured to transmit the second reference voltage signal ([0055]: “power rail 34 is conducted with the common lower supply voltage VSS of the first power supply”) to the second isolation circuit,
wherein the antenna circuit is disposed between (portion 200 of circuit 140 is “between” in the X direction) the first conductive segment and the second conductive segment.
Regarding claim 6, Lu discloses the semiconductor device of claim 5 (Fig. 4B), wherein
the first isolation circuit comprises a first gate structure (42p) configured to receive the first reference voltage signal (“configured” is shown by VG on 32),
the second isolation circuit comprises a second gate structure (41p) configured to receive the first reference voltage signal (“configured” is shown by VG on 32), and
the second conductive segment, the second gate structure, the first gate structure and the first conductive segment are arranged in order (at least some portions of segment 34 are sandwiching gates 41p and 42p in the claimed sequence).
Regarding claim 7, Lu discloses the semiconductor device of claim 1 (Fig. 4B), wherein the first isolation circuit comprises:
a first gate portion (42n) corresponding to a first transistor (Fig. 4A: transistor T2n) of the first isolation circuit;
a first source/drain structure (64n) corresponding to the first transistor, and configured to receive the second reference voltage signal (schematically shown in Fig. 4A; [0049]: “lower supply voltage”);
a second gate portion (42p) corresponding to a second transistor (Fig. 4A: transistor T2p) of the first isolation circuit, and separated from the first gate portion (“separated” in the Y direction); and
a second source/drain structure (64p) corresponding to the second transistor, and configured to receive the first reference voltage signal (schematically shown in Fig. 4A; [0049]: “upper supply voltage”).
Regarding claim 8 as noted in the 112(b) rejection, Lu discloses the semiconductor device of claim 7 (Fig. 4C), wherein the first isolation circuit comprises:
a third source/drain structure (62n) corresponding to the first transistor, and coupled (capacitively “coupled” through 84 and 62p) to the second gate portion; and
a fourth source/drain structure (62p) corresponding to the second transistor, and coupled (capacitively “coupled” through 84 and 62n) to the first gate portion.
Regarding claim 9, Lu discloses the semiconductor device of claim 7 (Fig. 4A), further comprising a second isolation circuit (See annotated figure) configured to isolate the antenna circuit (transistors T5p/T3p/T1p/T3n/T1n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured to isolate…” circuit 210A from circuit 200), the second isolation circuit comprising:
a third gate portion (41n) corresponding to a third transistor (Fig. 4A: transistor T1n) of the second isolation circuit;
a third source/drain structure (63n) corresponding to the third transistor, and configured to receive the second reference voltage signal (schematically shown in Fig. 4A; [0049]: “lower supply voltage”);
a fourth gate portion (41p) corresponding to a fourth transistor (Fig. 4A: transistor T1p) of the second isolation circuit, and separated from the third gate portion (“separated” in the Y direction); and
a fourth source/drain structure (63p) corresponding to the fourth transistor, and configured to receive the first reference voltage signal (schematically shown in Fig. 4A; [0049]: “upper supply voltage”),
wherein the fourth gate portion, the fourth source/drain structure, the antenna circuit, the second source/drain structure and the second gate portion are arranged in order (X direction order is shown).
Regarding independent claim 21, Lu discloses a method (Fig. 4A), comprising:
forming a function circuit (210B) configured to receive a first reference voltage signal (NET1/NET2. Note: Fig. 4A shows these signal annotations inverted from the specification [0056]: “correspondingly connected to some signal voltages”) and a second reference voltage signal (VSS; [0049]: “lower supply voltage”; [0032]: “the third power domain”);
forming an antenna circuit (140) configured to receive the first reference voltage signal (140 as cited includes the entire circuitry, and thus is including all voltages) to share charges with the function circuit (“share charges” either capacitively by the gates of transistors, or conductively through the transistors); and
forming a first isolation circuit (See annotated figure) disposed between the function circuit and the antenna circuit, and configured to receive the second reference voltage signal (VSS passes through the 1st isolation circuit) to isolate the function circuit and the antenna circuit from each other (transistors T6p/T2p/T4n/T2n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured…to isolate…” circuit 210B from circuit 200).
Regarding claim 22, Lu discloses the method of claim 21 (Fig. 4B), wherein forming the first isolation circuit comprises:
forming a first gate structure (44n) corresponding to a first transistor (T4n) of the first isolation circuit, and configured to receive the first reference voltage signal ([0056]: “T4n…correspondingly connected to…NET2”); and
forming a first source/drain structure (66n) corresponding to the first transistor, and configured to receive the second reference voltage signal ([0049]: “lower supply voltage VSS”).
Regarding claim 25, Lu discloses the method of claim 22 (Fig, 4A), further comprising:
forming a second isolation circuit (See annotated figure) configured to isolate the antenna circuit (transistors T5p/T3p/T1p/T3n/T1n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured to isolate…” circuit 210A from circuit 200);
forming a first conductive segment (Fig. 4B: segment 34, See annotated figure) configured to transmit the second reference voltage signal ([0055]: “power rail 34 is conducted with the common lower supply voltage VSS of the first power supply”) to the first isolation circuit; and
forming a second conductive segment (VG) configured to transmit the second reference voltage signal ([0055]: “power rail 34 is conducted with the common lower supply voltage VSS of the first power supply”) to the second isolation circuit,
wherein the antenna circuit is disposed between (portion 200 of circuit 140 is “between” in the X direction) the first conductive segment and the second conductive segment.
Note that claims 21 and 25 were previously addressed above, however, they’re being addressed differently here based on the reading of the reference, particularly to the assignment of the “first reference voltage signal” in order to address the dependent claim 26.
Regarding independent claim 21, Lu discloses a method (Fig. 4A), comprising:
forming a function circuit (210B) configured to receive a first reference voltage signal (VDD2) and a second reference voltage signal (VSS; [0049]: “lower supply voltage”; [0032]: “the third power domain”);
forming an antenna circuit (140) configured to receive the first reference voltage signal (140 as cited includes the entire circuitry, and thus is including all voltages) to share charges with the function circuit (“share charges” either capacitively by the gates of transistors, or conductively through the transistors); and
forming a first isolation circuit (See annotated figure) disposed between the function circuit and the antenna circuit, and configured to receive the second reference voltage signal (VSS passes through the 1st isolation circuit) to isolate the function circuit and the antenna circuit from each other (transistors T6p/T2p/T4n/T2n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured…to isolate…” circuit 210B from circuit 200).
Regarding claim 25, Lu discloses the method of claim 22 (Fig, 4A), further comprising:
forming a second isolation circuit (See annotated figure) configured to isolate the antenna circuit (transistors T5p/T3p/T1p/T3n/T1n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured to isolate…” circuit 210A from circuit 200);
forming a first conductive segment (Fig. 4B: a corresponding segment/portion of 34, See annotated figure) configured to transmit the second reference voltage signal ([0055]: “power rail 34 is conducted with the common lower supply voltage VSS of the first power supply”) to the first isolation circuit; and
forming a second conductive segment (a corresponding segment/portion of 34) configured to transmit the second reference voltage signal ([0055]: “power rail 34 is conducted with the common lower supply voltage VSS of the first power supply”) to the second isolation circuit,
wherein the antenna circuit is disposed between (portion 200 of circuit 140 is “between” in the X direction) the first conductive segment and the second conductive segment.
Regarding claim 26, Lu discloses the method of claim 25 (Fig. 4B), wherein
forming the first isolation circuit comprises forming a first gate structure (42p) configured to receive the first reference voltage signal (“configured” is shown by VG on 32),
forming the second isolation circuit comprises forming a second gate structure (41p) configured to receive the first reference voltage signal (“configured” is shown by VG on 32), and
the second conductive segment, the second gate structure, the first gate structure and the first conductive segment are arranged in order (at least some portions of segment 34 are sandwiching gates 41p and 42p in the claimed sequence).
Regarding claim 27, Lu discloses the method of claim 21 (Fig. 4B), wherein forming the first isolation circuit comprises:
forming a first gate portion (42n) corresponding to a first transistor (Fig. 4A: transistor T2n) of the first isolation circuit;
forming a first source/drain structure (64n) corresponding to the first transistor, and configured to receive the second reference voltage signal (schematically shown in Fig. 4A; [0049]: “lower supply voltage”);
forming a second gate portion (42p) corresponding to a second transistor (Fig. 4A: transistor T2p) of the first isolation circuit, and separated from the first gate portion (“separated” in the Y direction); and
forming a second source/drain structure (64p) corresponding to the second transistor, and configured to receive the first reference voltage signal l (schematically shown in Fig. 4A; [0049]: “upper supply voltage”).
Regarding claim 28 as noted in the 112(b) rejection, Lu discloses the method of claim 27 (Fig. 4C), wherein forming the first isolation circuit comprises:
forming a third source/drain structure (62n) corresponding to the first transistor, and coupled (capacitively “coupled” through 84 and 62p) to the second gate portion; and
forming a fourth source/drain structure (62p) corresponding to the second transistor, and coupled (capacitively “coupled” through 84 and 62n) to the second gate portion.
Regarding claim 29, Lu discloses the method of claim 27 (Fig. 4A), further comprising forming a second isolation circuit (See annotated figure) configured to isolate the antenna circuit (transistors T5p/T3p/T1p/T3n/T1n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured to isolate…” circuit 210A from circuit 200), forming the second isolation circuit comprising:
forming a third gate portion (41n) corresponding to a third transistor (Fig. 4A: transistor T1n) of the second isolation circuit;
forming a third source/drain structure (63n) corresponding to the third transistor, and configured to receive the second reference voltage signal (schematically shown in Fig. 4A; [0049]: “lower supply voltage”);
forming a fourth gate portion (41p) corresponding to a fourth transistor (Fig. 4A: transistor T1p) of the second isolation circuit, and separated from the third gate portion (“separate” in the Y direction); and
forming a fourth source/drain structure (63p) corresponding to the fourth transistor, and configured to receive the first reference voltage signal (schematically shown in Fig. 4A; [0049]: “upper supply voltage”),
wherein the fourth gate portion, the fourth source/drain structure, the antenna circuit, the second source/drain structure and the second gate portion are arranged in order (X direction order is shown).
Regarding independent claim 30, Lu discloses a semiconductor device (Fig. 4A), comprising:
a function circuit (210B) configured to receive a first reference voltage signal (VDD2) and a second reference voltage signal (VSS; [0049]: “lower supply voltage”; [0032]: “the third power domain”);
an antenna circuit (140) configured to receive the first reference voltage signal (140 as cited includes the entire circuitry, and thus is including all voltages) to share charges with the function circuit (“share charges” either capacitively by the gates of transistors, or conductively through the transistors);
a first isolation circuit (See annotated figure) disposed between the function circuit and the antenna circuit, and configured to receive the second reference voltage signal (VSS passes through the 1st isolation circuit) to isolate the function circuit and the antenna circuit from each other (transistors T6p/T2p/T4n/T2n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured…to isolate…” circuit 210B from circuit 200); and
a second isolation circuit (See annotated figure) configured to isolate the antenna circuit (transistors T5p/T3p/T1p/T3n/T1n are capable of preventing the flow of VSS and any other electricity through their channels under at least some electrical conditions, and are thus “configured to isolate…” circuit 210A from circuit 200), and configured to receive the second reference voltage signal (VSS passes through the 2nd isolation circuit),
wherein the antenna circuit is disposed between (portion 200 of circuit 140 is “between” in the X direction) the first isolation circuit and the second isolation circuit.
Regarding claim 31, Lu discloses the semiconductor device of claim 30 (Fig. 4B), further comprising:
a first conductive segment (32) configured to transmit the first reference voltage signal and coupled to each of the first isolation circuit and the second isolation circuit; and
a second conductive segment (34) configured to transmit the second reference voltage signal and coupled to each of the first isolation circuit and the second isolation circuit,
wherein the antenna circuit is disposed between (“between” in the Y direction) the first conductive segment and the second conductive segment.
Allowable Subject Matter
Claims 3-4 and 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 3 is the inclusion of the limitation “a first conductive segment crossing over and coupled to the first source/drain structure, and configured to transmit the second reference voltage signal to the first source/drain structure; and a second conductive segment corresponding to the first transistor, wherein the first gate structure is disposed between the first conductive segment and the second conductive segment, and the first conductive segment is longer than the second conductive segment” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first conductive segment” and “second conductive segment” and all other required dimensional, arrangement, and functional configurations of the claim in combination with all other limitations in intervening claims 2 and 1.
The primary reason for the allowable subject matter of claim 4 is the inclusion of the limitation “a first conductive segment coupled to source/drain terminals of transistors of the antenna circuit; and a second conductive segment coupled to each of gate terminals of the transistors of the antenna circuit and the first gate structure, wherein the second conductive segment is longer than the first conductive segment along a direction, and the first isolation circuit is disposed between the function circuit and the antenna circuit along the direction” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first conductive segment” and “second conductive segment” and all other required dimensional, arrangement, and functional configurations of the claim in combination with all other limitations in intervening claims 2 and 1.
The primary reason for the allowable subject matter of claim 23 is the inclusion of the limitation “forming a first conductive segment crossing over and coupled to the first source/drain structure, and configured to transmit the second reference voltage signal to the first source/drain structure; and forming a second conductive segment corresponding to the first transistor, wherein the first gate structure is disposed between the first conductive segment and the second conductive segment, and the first conductive segment is longer than the second conductive segment” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first conductive segment” and “second conductive segment” and all other required dimensional, arrangement, and functional configurations of the claim in combination with all other limitations in intervening claims 22 and 21.
The primary reason for the allowable subject matter of claim 24 is the inclusion of the limitation “forming a first conductive segment coupled to source/drain terminals of transistors of the antenna circuit; and forming a second conductive segment coupled to each of gate terminals of the transistors of the antenna circuit and the first gate structure, wherein the second conductive segment is longer than the first conductive segment along a direction, and the first isolation circuit is disposed between the function circuit and the antenna circuit along the direction” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first conductive segment” and “second conductive segment” and all other required dimensional, arrangement, and functional configurations of the claim in combination with all other limitations in intervening claims 22 and 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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