DETAILED ACTION
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II (claims 11-20) in the reply filed on July 6, 2026 is acknowledged. Claims 1-10 drawn to non-elected invention have been canceled.
Information Disclosure Statement
The information disclosure statement (IDS) filed on May 8, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Objections
Claim 15 is objected to because of the following informality:
In claim 15, lines 2-5, “the other surface of the first barrier layer contacting the other surface of the semiconductor material layer disposed on a sidewall of each of the plurality of active areas are conformal” should read --the other surface of the first barrier layer contacting the other surface of the semiconductor material layer disposed on a sidewall of each of the plurality of active areas is conformal-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 12 recites the feature “a top surface of the semiconductor material layer is higher than a top surface of the substrate” lines 1-2. It is unclear how “a top surface of the semiconductor material layer” of claim 12 relates back to “a top surface of the semiconductor material layer” in lines 8-9 of the base claim 11. For the examination purpose, the above feature is interpreted as disclosed in prior art.
Claim 13 recites the feature “a top surface of the semiconductor material layer is even and coplanar with a top surface of the insulating layer” lines 1-2. It is unclear how “a top surface of the semiconductor material layer” of claim 12 relates back to “a top surface of the semiconductor material layer” in lines 8-9 of the base claim 11. For the examination purpose, the above feature is interpreted as disclosed in prior art.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-15, 18 and 19 are rejected under 35 U.S.C. 102(a)(1) or 35 U.S.C. 102(a)(2) as being anticipated by IM et al. US 2020/0402839.
Regarding claim 11, IM teaches a semiconductor structure (e.g., Fig. 3A, Fig. 4A, the description thereof; also see Fig. 3B, Figs. 5-6 and the description thereof for additional details), comprising:
a plurality of active areas (e.g., 101, Fig. 3A), disposed in a substrate (e.g., 100, Fig. 3A) and surrounded by a semiconductor material layer (e.g., 123, Fig. 3A, [57]), wherein a surface of the semiconductor material layer contacting each of the plurality of active areas is rough (e.g., S1 of 123, Fig. 3A, Fig. 4A; [58]); and
a plurality of insulation areas (e.g., insulation areas; see the annotated Fig. 3A), disposed in the substrate and surrounding each of the plurality of active areas (e.g., see the annotated Fig. 3A), wherein each of the plurality of insulation areas comprises the semiconductor material layer (e.g., portion of 123 in the insulation area (discussed above); see the annotated Fig. 3A), a first barrier layer (e.g., 131, Fig. 3A, Fig. 4A; [63]) on the semiconductor material layer and an insulating layer (e.g., 137, Fig. 3A, Fig. 4A; [57]) over the first barrier layer, and wherein a top surface of the semiconductor material layer and a bottom surface of the semiconductor material layer are rough (e.g., S2 and S1 of the portion of 123 in the insulation area (discussed above) are rough; [58]).
PNG
media_image1.png
422
804
media_image1.png
Greyscale
Annotated Fig. 3A of IM
Regarding claim 12, IM teaches the semiconductor structure of claim 11, wherein a top surface of the semiconductor material layer is higher than a top surface of the substrate (e.g., see the annotated Fig. 3A above; see the 112 rejection above).
Regarding claim 13, IM teaches the semiconductor structure of claim 11, wherein a top surface of the semiconductor material layer is even and coplanar with a top surface of the insulating layer (e.g., Fig. 3B; see the 112 rejection above).
Regarding claim 14, IM teaches the semiconductor structure of claim 11, wherein each of the plurality of insulation areas further comprises: a second barrier layer (e.g., 133 of silicon nitride layer, Fig. 4A, [57]), disposed between the first barrier layer and the insulating layer.
Regarding claim 15, IM teaches the semiconductor structure of claim 14, wherein one surface of the first barrier layer (e.g., one surface of 131 contacting a surface of 133 is even, Fig. 4A) contacting a surface of the second barrier layer is even, and the other surface of the first barrier layer (e.g., the other surface of 131 contacting S2 of 123 is conformal, Fig. 4A) contacting the other surface of the semiconductor material layer disposed on a sidewall of each of the plurality of active areas are conformal.
Regarding claim 18, IM teaches the semiconductor structure of claim 11, further comprising: a plurality of word line structures (e.g., word line structures each including WL, GCP and GL, Fig. 6D) extending through the insulation areas and the active areas, wherein each of the plurality of word line structures comprises: a conductive layer (e.g., WL, Fig. 6D) a cap layer (e.g., GCP, Fig. 6D), disposed on the conductive layer; and a dielectric liner layer (e.g., GL, Fig. 6D), surrounding the conductive layer and the cap layer; and a plurality of source/drain areas (e.g., 105, Fig. 6D), disposed in the plurality of active areas and disposed on opposite sides of each of the plurality of word line structures (e.g., Fig. 6D).
Regarding claim 19, IM teaches the semiconductor structure of claim 18, wherein a sidewall of an upper portion of each of the word line structures is surrounded by the semiconductor material layer (e.g., Fig. 6D; also see Fig. 6B, Fig. 6C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over IM et al. US 2020/0402839.
Regarding claim 16, IM teaches the semiconductor structure of claim 11 as discussed above.
IM does not explicitly teach wherein a thickness of the semiconductor material layer is from 55 angstroms to 80 angstroms.
IM, however, recognizes that a thickness of the semiconductor material layer 123 may have about 5 Å to about 50 Å (e.g., [38]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the structure of IM to have the claimed range since it has been held that where the criticality of the claimed range is not shown and the close conditions of a claim are disclosed in the prior art, a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. MPEP §2144.05.
Regarding claim 17, IM teaches the semiconductor structure of claim 11 as discussed above.
IM does not explicitly teach wherein a thickness of the first barrier layer is from 15 angstroms to 20 angstroms.
IM, however, recognizes that a thickness of the first barrier layer 131 may have about 10 Å to about 90 Å (e.g., [44]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the structure of IM to have the claimed range since it has been held that where the criticality of the claimed range is not shown and the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. MPEP § 2144.05.
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The art made of record and not applied to the rejection is considered pertinent to applicant's disclosure. It is cited primarily to show inventions relevant to the examination of the instant invention. For example, Chen et al. US 2003/0143802 relates to a semiconductor structure including a semiconductor material layer with a rough surface.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) OR 571-272-1000.
/BO B JANG/Primary Examiner, Art Unit 2818 September 19, 2026
Prosecution Insights