DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Restriction/Election filed on 09/02/2026.
Currently claims 1-25 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Group II, Species A, claims 1-2 and 5-6, in the reply filed on 09/02/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/09/2024 and 07/31/2025 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5-6 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 5, the limitation “alternative layers of silicon and silicon germanium extended horizontally between the first source/drain region and the third source/drain region” is indefinite. The term “alternative” has two reasonable readings: (i) layers that alternate in sequence (Si/SiGe/Si/SiGe…), or (ii) layers that are, in the alternative, either silicon or silicon germanium. The specification describes “vertically stacked epitaxial layers of a first material 140A and a second material 140B” with silicon as the first material and silicon germanium as the second material ([0100] – [0101]) but does not use or define “alternative layers.” Because the claim language admits of more than one reasonable scope, one of ordinary skill in the art would not be reasonably apprised of the metes and bounds of the claim. Claim 6 is rejected for depending on claim 5 and failing to cure the deficiency. For purposes of examination, as best understood, the limitation is interpreted as “alternating layers of silicon and silicon germanium.” Correction or clarification is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0088578 A1 (Thomson1) and further in view of US 2024/0105615 A1 (Lee1).
Regarding claim 1, Thomson1 teaches, a semiconductor device (integrated circuit configured with a lateral diode having both frontside and backside connections; Thomson1 Fig. 1c; [0047]), comprising:
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a diode (lateral diode formed by diffusion regions 103a-b, 107a-b and nanoribbons 101a; PIN diode; Thomson1 Figs. 1c, 1d; [0021], [0037], [0047] – [0048]),
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the diode comprising:
a first frontside contact (109b; contact, “provisioned during a frontside process and lands on one or more surfaces of each of diffusion regions 107a-b”; Thomson1 Fig. 1c; [0047]) over a first source/drain region (107b; source or drain region; Thomson1 Fig. 1c; [0035], [0037], [0047]);
a first backside contact (113; contact, “provisioned in dielectric layer 104 during a backside process”; Thomson1 Fig. 1c; [0047]); and
a first placeholder connected to a bottom surface of the first source/drain region - in Thomson1, dielectric layer 104 lies below the first source/drain region 107b (104; dielectric layer; Thomson1 Fig. 1c; [0035], [0047]); the placeholder is taught by Lee1, as set forth below.
But Thomson1 does not expressly teach, a first placeholder connected to a bottom surface of the first source/drain region.
However, in analogous art, Lee1 teaches, a first placeholder (P1; 1st placeholder structure, SiGe; Lee1 Figs. 7A, 26A; [0085] – [0087]) connected to a bottom surface of the first source/drain region (SD1; 1st source/drain region; Lee1 Figs. 10A, 26A; [0094], [0098]). The placeholder P1 being connected to the bottom surface of SD1 through blocking layer (181; blocking layer, epitaxial Si; Lee1 Figs. 8A, 26A; [0089] – [0090]). Lee1 forms the placeholder P1 below the frontside-contacted source/drain region SD1 so that SD1 is grown under the same conditions as the backside-contacted source/drain region SD2 and both have the same or substantially same height or size ([0096] – [0098]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Thomson1 and Lee1 before him/her, because forming a placeholder below the frontside-contacted source/drain region causes that source/drain region to be epitaxially grown under the same conditions as the backside-contacted source/drain region, yielding source/drain regions of the same or substantially same height or size and a stable and consistent device performance (Lee1 [0096]–[0098]), and retaining the placeholder in the finished device simplifies the manufacturing process (Lee1 [0156], [0166]); further, Thomson1 forms its diodes “in a fashion similar to transistor devices” and favors consistency of process with transistors formed in the logic area of the same die (Thomson1 [0021], [0039]). Absent this teaching in Thomson1, a person with ordinary skill in the art would be motivated to reach out to Lee1 while forming the lateral diode of Thomson1.
Regarding claim 2, the combination of Thomson1 and Lee1 teaches, the semiconductor device of claim 1, where Thomson1 teaches that transistor structures are formed simultaneously with the diodes in other locations of the same integrated circuit (e.g., the logic area of the device layer) (Thomson1 [0039], [0043]), and Lee1 teaches the transistor and its contacts and placeholder:
“further comprising a transistor (TR1; 1st nanosheet transistor; Lee1 Figs. 10A, 33A; [0097], [0162]), the transistor comprising: a second frontside contact (CA1; 1st MOL contact plug; Lee1 Figs. 19A, 26A; [0123], [0146]) over a second source/drain region (SD1; 1st source/drain region; Lee1 Figs. 10A, 26A; [0094]–[0098]); a second backside contact (BCA1; 1st backside contact plug; Lee1 Figs. 32A, 35A; [0158]–[0159], [0162]); and a second placeholder (P1; 1st placeholder structure; Lee1 Figs. 7A, 26A; [0085]–[0087], [0142]) connected to a bottom surface of the second source/drain region (SD1; 1st source/drain region, via blocking layer 181; Lee1 Figs. 8A, 26A; [0089], [0094]).”
The placeholder P1 of the transistor TR1 is retained for the reasons and with the rationale set forth for claim 1 (Lee1 [0096] – [0098], [0156], [0165] – [0166]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Thomson1 and Lee1 before him/her, (1) because Thomson1 expressly contemplates forming transistor structures in the logic area of the same die using processing consistent with the diode processing (Thomson1 [0039]), and Lee1 provides such a nanosheet transistor having a frontside contact, a backside contact and a placeholder below the frontside-contacted source/drain region for uniform source/drain growth and consistent device performance (Lee1 [0096]–[0098], [0162]); (2) since the modification amounts to a combination of known elements according to known methods (MPEP 2143(I)(A)); and (3) with a reasonable expectation of success, yielding the predictable result of a single die on which the lateral diode of Thomson1 and the nanosheet transistor of Lee1 are co-integrated, each having a frontside contact, a backside contact and a placeholder at the bottom of a source/drain region. Absent this teaching in Thomson1, a person with ordinary skill in the art would be motivated to reach out to Lee1 while forming the integrated circuit of Thomson1.
Regarding claim 5, the combination of Thomson1 and Lee1 teaches, the semiconductor device of claim 1, wherein the diode further includes:
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a third source/drain region (103b; source or drain region; Thomson1 Fig. 1c; [0035], [0037]); and
alternative layers of silicon (101a; nanoribbons, “e.g., silicon”; Thomson1 Fig. 1c; [0034]) and silicon germanium (101b; semiconductor layers, “e.g., SiGe”, left unreleased; Thomson1 Fig. 1c; [0034]–[0035], [0037]) extended horizontally between the first source/drain region (107b; source or drain region; Thomson1 Fig. 1c; [0035]) and the third source/drain region (103b; source or drain region; Thomson1 Fig. 1c; [0035]).
Thomson1 teaches that the junction of the lower diode is provided by diffusion regions 103b and 107b “along with the lower two nanoribbons 101a laterally extending therebetween,” with the intervening layers 101b left in place ([0035], [0037]); the multilayer substrate 101 “includes alternating layers of semiconductor materials 101a (e.g., silicon) and 101b (e.g., SiGe)” ([0034]).
Regarding claim 6, the combination of Thomson1 and Lee1 teaches, the semiconductor device of claim 5, wherein the first source/drain region is an N-type source-drain region (107b; source or drain region, n-doped cathode region; Thomson1 Figs. 1c, 1d; [0037], [0041], [0048]) and the third source/drain region is a P-type source/drain region (103b; source or drain region, p-doped anode region; Thomson1 Figs. 1c, 1d; [0037], [0041], [0048]), or the first source/drain region is a P-type source-drain region and the third source/drain region is an N-type source/drain region.” Thomson1 further teaches that the polarities may be reversed ([0046], [0068]).
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2023/0163202 A1 (Lee2) - PNPN diode, N-well resistor or BJT formed in a nanosheet transistor structure, with frontside contact plugs on epitaxial source/drain regions and a backside (BSPDN) contact plug on the bottom surface of a doped region.
US 2022/0415877 A1 (Orr) - A semiconductor device is disclosed including a first interconnect and a second interconnect, a substrate between the first and second interconnects and one or more wells on the substrate on a first level. A second level includes a first fin and a second fin, each on the one or more wells, where the first fin and the one or more wells include dopants of a first conductivity type and the second fin includes a dopant of a second conductivity type. A third fin is over a first region between the substrate and the first interconnect, and a fourth fin is over a second region between the substrate and the second interconnect. A third interconnect is electrically coupled between the first interconnect and the first fin and a fourth interconnect is electrically coupled between the second interconnect and the second fin.
US 2020/0403007 A1 (Thomson2) - A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
10/14/2026
