Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group II (claims 8-16) in the reply filed on 5/26/26 is acknowledged. Claims 1-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Election was made without traverse in the reply filed on 5/26/26.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Semiconductor device with Air Gaps in a Replacement Metal Gate and method for fabricating the same”
because the invention is directed to forming air gaps within a replacement metal gate structure to improve device performance, the proposed title more accurately describes the disclosed invention and is consistent with the claimed subject matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (US 20200127109).
Regarding claim 8. Fig 20 and Fig 21 ([0027]-[0028] (both are the same embodiment but different cross-sectional view) of Wang discloses A semiconductor device [0027]-[0028], comprising:
a metal gate 166 [0040] on a substrate 110/130 [0032];
a spacer 158 [0035] adjacent to the metal gate;
an interlayer dielectric (ILD) layer 160 around the metal gate [0036] (Fig 21); and
a first air gap 184 (Fig 20: left 184) adjacent to one side of the metal gate and between the spacer and the metal gate (Fig 20).
Regarding claim 9. Wang discloses The semiconductor device of claim 8, further comprising:
a second air gap 184 (Fig 20: right side) adjacent to another side of the metal gate and between the spacer and the metal gate (Fig 21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20200127109) in view of Cheng (US 20200279933; hereinafter Cheng-933).
Regarding claim 10. Wang discloses The semiconductor device of claim 9, Wang discloses a replacement metal gate structure including a gate dielectric layer 150, a work function metal (WFM) layer 156 disposed on the gate dielectric layer, and a gate metal 166 disposed on the WFM layer. Thus, Wang's metallic gate portion includes two distinct metal layers, namely the WFM layer 156 and the overlying gate metal 166. Wang further discloses that gate metal 166 may comprise tungsten (W), beryllium (Be), gold (Au), platinum (Pt), palladium (Pd), and/or other metallic materials conventionally used in the metallic portion of a gate structure [0040].
But Wang does not expressly disclose that gate dielectric layer 150 is a high-k dielectric layer or that gate metal 166 is a low resistance metal layer, as claimed.
However, Cheng-933 discloses a replacement metal gate including a high-k dielectric layer, a WFM layer disposed on the high-k dielectric layer, and a low resistance metal layer disposed on the WFM layer [0053]-[0054].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang's gate structure by employing the high-k dielectric layer and low resistance metal layer taught by Cheng-933 to improve gate performance by providing enhanced gate dielectric characteristics while reducing gate resistance.
Regarding claim 13. Wang in view of Cheng-933 discloses The semiconductor device of claim 10, Further, Wang discloses that the top surface of the metal gate is lower than the top surface of the interlayer dielectric (ILD), as claimed. Specifically, Wang discloses a replacement metal gate including gate dielectric layer 150, work function metal (WFM) layer 156, and conductive gate metal 166, wherein the metal gate is recessed below the top surface of interlayer dielectric (ILD) layer 160, thereby meeting the claimed limitation.
Regarding claim 14. Wang in view of Cheng-933 discloses The semiconductor device of claim 10, Further, Wang discloses an air gap, a buffer layer, and a hard mask, as claimed. Specifically, Wang discloses forming air gap 184 adjacent the replacement metal gate (Figs. 18-20, [0046]). Wang further discloses forming gate cap 190 on gate metal 166, followed by forming ILD 202 thereon. Wang also discloses forming contact openings using an additional mask on predetermined portions of ILD 202 [0050]. Accordingly, ILD 202 corresponds to the claimed buffer layer, and the additional mask corresponds to the claimed hard mask.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20200127109) in view of Cheng (US 20200279933; hereinafter Cheng-933), and further in view of Cheng (US 20220254927, hereinafter Cheng-927).
Regarding claim 11. Wang in view of Cheng-933 discloses The semiconductor device of claim 10. But Wang in view of Cheng-933 does not expressly disclose that a top surface of the work function metal (WFM) layer is lower than a top surface of the high-k dielectric layer.
However, Cheng -927 discloses a gate stack including an interfacial oxide layer 136, a high-k (HK) gate dielectric layer 138, a WFM layer 140 disposed on the HK gate dielectric layer 138, and a gate metal fill layer 142 disposed on the WFM layer 140. Cheng-927 further discloses that the HK gate dielectric layer 138 extends above the top surfaces of the WFM layer 140 and the gate metal fill layer 142 by a thickness T1, thereby disclosing that the top surface of the WFM layer is lower than the top surface of the high-k dielectric layer (Fig 1B, [0032], [0036]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate structure of Wang, as modified by Cheng-933, to employ the relative arrangement of the high-k dielectric layer and WFM layer taught by Cheng-927 because Cheng-927 teaches that this gate profile is obtained during formation of the replacement gate stack and represents a suitable gate stack configuration for semiconductor device fabrication.
Regarding claim 12. Wang in view of Cheng-933 discloses Wang discloses The semiconductor device of claim 10. But Wang in view of Cheng-933 does not expressly disclose wherein a top surface of the WFM layer is lower than a top surface of the low resistance metal layer.
However, Cheng-927 discloses a gate stack including a high-k dielectric layer 138, a WFM layer 140, and a gate metal fill layer 142, wherein the gate metal fill layer may comprise tungsten, titanium, silver, ruthenium, molybdenum, copper, cobalt, aluminum, iridium, nickel, or combinations thereof. Cheng-927 further discloses that the high-k dielectric layer 138 extends above the top surfaces of the WFM layer 140 and the gate metal fill layer 142 by a thickness T1, thereby disclosing that the top surface of the low resistance metal layer is lower than the top surface of the high-k dielectric layer (Fig 1B, [0034]-[0036]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate structure of Wang, as modified by Cheng-933, to employ the relative arrangement of the high-k dielectric layer and WFM layer taught by Cheng-927 because Cheng-927 teaches that this gate profile is obtained during formation of the replacement gate stack and represents a suitable gate stack configuration for semiconductor device fabrication.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20200127109) in view of Cheng (US 20200279933; hereinafter Cheng-933), and further in view Yao (US 20210242324)
Regarding claim 15. Wang in view of Cheng-933 discloses Wang discloses The semiconductor device of claim 10. But Wang in view of Cheng-933 does not expressly disclose wherein the first air gap is between the high-k dielectric layer and the low resistance metal layer.
However, Yao discloses a FinFET including a first air gap 258 (left side) disposed between high-k dielectric layer 254 and gate electrode 256 (Fig. 19; [0028]). Yao further discloses that gate electrode 256 may include multiple layers, including one or more work function layers, one or more glue/barrier layers, and one or more metal fill (bulk) layers, wherein the metal fill layer may comprise aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), or other conductive materials [0043]. Accordingly, the metal fill layer of gate electrode 256 corresponds to the claimed low resistance metal layer, and first air gap 258 is disposed between the high-k dielectric layer 254 and the low resistance metal layer.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate structure of Wang as taught by Cheng-933 to incorporate the air-gap configuration taught by Yao in order to reduce parasitic capacitance and improve transistor performance.
Regarding claim 16. Wang in view of Cheng-933 discloses Wang discloses The semiconductor device of claim 10. But Wang in view of Cheng-933 does not expressly disclose wherein the second air gap is between the high-k dielectric layer and the low resistance metal layer.
However, Yao discloses a FinFET including a second air gap 258 (right side) disposed between high-k dielectric layer 254 and gate electrode 256 (Fig. 19; [0028]). Yao further discloses that gate electrode 256 may include multiple layers, including one or more work function layers, one or more glue/barrier layers, and one or more metal fill (bulk) layers, wherein the metal fill layer may comprise aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), or other conductive materials [0043]. Accordingly, the metal fill layer of gate electrode 256 corresponds to the claimed low resistance metal layer, and the second air gap 258 is disposed between the high-k dielectric layer 254 and the low resistance metal layer.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate structure of Wang as taught by Cheng-933 to incorporate the air-gap configuration taught by Yao in order to reduce parasitic capacitance and improve transistor performance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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