DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 is objected to because of the following informalities.
Claim 5 recited the term of “The” in line 2. The alphabet of the term “The” is incorrect.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 7, 9, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (U.S. 2023/0380130 A1, hereinafter refer to Chou) in view of Kim et al. (U.S. 2025/0098327 A1, hereinafter refer to Kim).
Regarding Claim 1: Chou discloses a semiconductor structure (see Chou, Figs.5-6D as shown below and ¶ [0018]), comprising:
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a first circuit in a first cell region (100A), the first circuit comprising a first n-type nanostructure transistor (PD) and a first p-type nanostructure transistor (PU) (see Chou, Figs.5-6D as shown above and ¶ [0035]- ¶ [0044]);
a first contact plug (226) electrically connected to drain nodes of the first n-type nanostructure transistor (PD) and the first p-type nanostructure transistor (PU) (see Chou, Figs.5-6D as shown above and ¶ [0035]- ¶ [0044]);
a first metal layer (228) over the first contact plug (226) (see Chou, Figs.5-6D as shown above and ¶ [0035]- ¶ [0044]); and
Chou is silent upon explicitly disclosing wherein a first metal layer over the first contact plug and comprising a first line and a second line electrically connected to the first contact plug; and
a second metal layer over the first metal layer and comprising a third line electrically connected to both the first line and the second line.
For support see Kim, which teaches wherein a first metal layer (M1) over the first contact plug (CA) and comprising a first line and a second line electrically connected to the first contact plug (CA) (see Kim, Fig.7A as shown below, ¶ [0056]- ¶ [0059], and ¶ [0071]); and
a second metal layer (M2) over the first metal layer (M1) and comprising a third line electrically connected to both the first line and the second line (see Kim, Fig.7A as shown below, ¶ [0056]- ¶ [0059], and ¶ [0071]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chou and Kim to enable first metal layer over the first contact plug and comprising a first line and a second line electrically connected to the first contact plug and a second metal layer over the first metal layer and comprising a third line electrically connected to both the first line and the second line as taught by Kim in order to electrically connect the source/drain regions SD the second metal layer through the source/drain contacts CA and first metal layer.
Regarding Claim 2: Chou as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Chou and Kim further teaches wherein the third line at least partially overlaps the first contact plug (CA) (see Kim, Fig.7A as shown above).
Regarding Claim 3: Chou as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Chou and Kim further teaches wherein a first via (VA) interposed between the first line (M1) and the first contact plug (CA) (see Kim, Fig.7A as shown above);
a second via (VA) interposed between the second line (M1) and the first contact plug (CA) (see Kim, Fig.7A as shown above);
a third via (V1) interposed between the first line (M1) and the third metal line (M2), wherein the third via (V1) at least partially overlaps the first via (VA) (see Kim, Fig.7A as shown above); and
a fourth via (V1) interposed between the second line (M1) and the third metal line (M2), wherein the fourth via (V1) at least partially overlaps the second via (VA) (see Kim, Fig.7A as shown above).
Regarding Claim 7: Chou as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Chou and Kim further teaches wherein the first metal layer further comprises:
a Vss power rail electrically connected to source nodes of the first n-type nanostructure transistor (PD) of the first circuit and the second n-type nanostructure transistor (PD) of the second circuit (see Chou, Fig.2); and
a Vdd power rail electrically connected to source nodes of the first p-type nanostructure transistor (PU) of the first circuit and the second p-type nanostructure transistor (PU) of the second circuit (see Chou, Fig.2).
Regarding Claim 9: Chou as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Chou and Kim further teaches wherein the first metal layer (M1) further comprises a fourth line electrically connected to the first contact plug (CA) and the third line of the second metal layer (M2) (see Kim, Fig.7A as shown above).
Regarding Claim 16: Chou discloses a semiconductor structure (see Chou, Figs.5-6D as shown above and ¶ [0018]), comprising:
a first gate stack (208A) wrapping around a first plurality of nanostructures (220) and a second plurality of nanostructures (220) (see Chou, Figs.5-6D as shown above);
a first source/drain feature (218) and a second source/drain feature (218) adjoining the first plurality of nanostructures (220) and the second plurality of nanostructures (220) (see Chou, Figs.5-6D as shown above), respectively;
a first contact plug (226C) on both the first source/drain feature (218) and the second source/drain feature (218) (see Chou, Figs.5-6D as shown above).
Chou is silent upon explicitly disclosing wherein a first via and a second via on the first contact plug;
a first metal line and a second metal line on the first via and the second via, respectively;
a third via and a fourth via on the first metal line and the second metal line, respectively; and a third metal line on both the third via and the fourth via.
For support see Kim, which teaches wherein a first via (VA) and a second via (VA) on the first contact plug (CA) (see Kim, Fig.7A as shown above, ¶ [0056]- ¶ [0059], and ¶ [0071]);
a first metal line (M1) and a second metal line (M2) on the first via (VA) and the second via (VA), respectively (see Kim, Fig.7A as shown above, ¶ [0056]- ¶ [0059], and ¶ [0071]);
a third via (V2) and a fourth via (V2) on the first metal line (M1) and the second metal line (M2), respectively (see Kim, Fig.7A as shown above, ¶ [0056]- ¶ [0059], and ¶ [0071]); and
a third metal line (M3) on both the third via (V2) and the fourth via (V2) (see Kim, Fig.7A as shown above, ¶ [0056]- ¶ [0059], and ¶ [0071]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chou and Kim to enable the first via and the second via on the first contact plug, the first metal line and the second metal line on the first via and the second via, respectively, and the third via and the fourth via on the first metal line and the second metal line as taught by Kim in order to electrically connect the source/drain regions SD the second metal layer through the source/drain contacts CA and first metal layer.
Regarding Claim 20: Chou as modified teaches a semiconductor structure as set forth in claim 16 as above. The combination of Chou and Kim further teaches wherein a first dielectric isolation structure (204) below the first source/drain feature (218) (see Chou, Figs.5-6D as shown above).
Claim(s) 4-6 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (U.S. 2023/0380130 A1, hereinafter refer to Chou) and Kim et al. (U.S. 2025/0098327 A1, hereinafter refer to Kim) as applied to claims 1 and 16 above, and further in view of Lee et al. (U.S. 2023/0189496 A1, hereinafter refer to Lee).
Regarding Claim 4: Chou as modified teaches a semiconductor structure as applied to claim 1 above. The combination of Chou and Kim further teaches wherein a second circuit in a second cell region (100B), the second circuit comprising a second n-type nanostructure transistor (PD) and a second p-type nanostructure transistor (PU) (see Chou, Figs.5-6D as shown above and ¶ [0035]- ¶ [0044]); and
a second contact plug (226) electrically connected to drain nodes of the second n-type nanostructure transistor (PD) and the second p-type nanostructure transistor (PU) (see Chou, Figs.5-6D as shown above and ¶ [0035]- ¶ [0044]);
wherein: the first n-type nanostructure transistor (PD) of the first circuit (100A) includes a first plurality of nanostructures having a first width in a horizontal direction that is parallel to a longitudinal axis of the first contact plug (226) (see Chou, Figs.5-6D as shown above and ¶ [0035]- ¶ [0044]), and
the second n-type nanostructure transistor (PD) of the second circuit (100B) includes a second plurality of nanostructures having a second width in the horizontal direction (see Chou, Figs.5-6D as shown above and ¶ [0035]- ¶ [0044]).
The combination of Chou and Kim is silent upon explicitly disclosing wherein the second width is less than the first width.
For support see Lee, which teaches wherein the second width (W1) is less than the first width (W2) (see Lee, Fig.7 as shown below and ¶ [0022]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chou, Kim, and Lee to enable the second width of Chou to be less than the first width as taught by Lee in order to provide superior channel electrostatics control.
Regarding Claim 5: Chou as modified teaches a semiconductor structure as set forth in claim 4 as above. The combination of Chou, Kim, and Lee further teaches wherein The second p-type nanostructure transistor (PU) of the first circuit includes a third plurality of nanostructures (220) having a third width in the first horizontal direction (see Chou, Figs.5-6D as shown above), and
the second p-type nanostructure transistor (PU) of the second circuit includes a fourth plurality of nanostructures (220) having a fourth width in the first horizontal direction (see Chou, Figs.5-6D as shown above), and
the fourth width (W1) is less than the third width (W2) (see Lee, Fig.7 as shown above).
Regarding Claim 6: Chou as modified teaches a semiconductor structure as set forth in claim 4 as above. The combination of Chou, Kim, and Lee further teaches wherein a ratio of the first width (W2) to the second width (W1) is in a range from about 1.5 to about 8 (see Lee, Fig.7 as shown above and ¶ [0033]).
Regarding Claim 17: Chou as modified teaches a semiconductor structure as applied to claim 16 above. The combination of Chou and Kim further teaches wherein a second gate stack (208E) wrapping around a third plurality of nanostructures (220) and a fourth plurality of nanostructures (220), wherein in a horizontal direction that is parallel to a longitudinal direction of the first gate stack (208A) (see Chou, Figs.5-6D as shown above),
a third source/drain feature (218) and a fourth source/drain feature (218) adjoining the third plurality of nanostructures (220) and the fourth plurality of nanostructures (220), respectively (see Chou, Figs.5-6D as shown above); and
a second contact plug (226C) on both the third source/drain feature (218) and the fourth source/drain feature (218) (see Chou, Figs.5-6D as shown above).
The combination of Chou and Kim is silent upon explicitly disclosing wherein a third plurality of nanostructures is narrower than the first third plurality of nanostructures and the fourth plurality of nanostructures is narrower than the second plurality of nanostructures.
For support see Lee, which teaches wherein a third plurality of nanostructures (W1) is narrower than the first third plurality of nanostructures (W2) and the fourth plurality of nanostructures (W1) is narrower than the second plurality of nanostructures (W2) (see Lee, Fig.7 as shown above and ¶ [0022]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chou, Kim, and Lee to enable the third plurality of nanostructures narrower than the first third plurality of nanostructures and the fourth plurality of nanostructures narrower than the second plurality of nanostructures as taught by Lee in order to provide superior channel electrostatics control.
The combination of Chou, Kim, and Lee is silent upon explicitly disclosing wherein in the horizontal direction, the second contact plug is shorter than the first contact plug.
However, practicing the combination of Chou, Kim, and Lee to modify the Chou’s third plurality of nanostructures to be narrower than the first third plurality of nanostructures and the fourth plurality of nanostructures to be narrower than the second plurality of nanostructures as taught by Lee necessarily results the in the horizontal direction, the Chou’s the second contact plug to be shorter than the first contact plug as now specified in claim 17.
Regarding Claim 18: Chou as modified teaches a semiconductor structure as set forth in claim 17 as above. The combination of Chou, Kim, and Lee further teaches wherein the first plurality of nanostructures and the third plurality of nanostructures are located in a p-type well (202B), and the second plurality of nanostructures and the fourth plurality of nanostructures are located in an n-type well (202A) (see Chou, Figs.5-6D as shown above).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (U.S. 2023/0380130 A1, hereinafter refer to Chou) and Kim et al. (U.S. 2025/0098327 A1, hereinafter refer to Kim) as applied to claim 1 above, and further in view of Liaw et al. (U.S. 2021/0202498 A1, hereinafter refer to Liaw).
Regarding Claim 8: Chou as modified teaches a semiconductor structure as applied to claim 1 above. The combination of Chou and Kim further teaches wherein the first cell region (100A) abuts the second cell region (100B) (see Chou, Figs.5-6D as shown above).
The combination of Chou and Kim is silent upon explicitly disclosing wherein the semiconductor structure further comprises: a fin-cut structure on a boundary between the first cell region and the second cell region.
For support see Liaw, which teaches wherein the semiconductor structure further comprises: a fin-cut structure (240) on a boundary between the first cell region (Sy-1) and the second cell region (Sy-2) (see Liaw, Figs.8 and 11 as shown below, ¶ [0040], and ¶ [0045]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chou, Kim, and Liaw to enable the semiconductor structure further to comprise a fin-cut structure on a boundary between the first cell region and the second cell region as taught by Liaw in order to truncating the p-type fins and n-type fin and reducing a gate pitch between adjacent gate stacks.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (U.S. 2023/0380130 A1, hereinafter refer to Chou), Kim et al. (U.S. 2025/0098327 A1, hereinafter refer to Kim), and Lee et al. (U.S. 2023/0189496 A1, hereinafter refer to Lee) as applied to claims 1 and 16 above, and further in view of Liaw et al. (U.S. 2021/0202498 A1, hereinafter refer to Liaw).
Regarding Claim 19: Chou as modified teaches a semiconductor structure as applied to claim 17 above. The combination of Chou, Kim, and Lee is silent upon explicitly disclosing wherein a first lower fin element continuously extending under the first plurality of nanostructures and the third plurality of nanostructures; and
a fin-cut structure interposed between the first gate stack and the second gate stack and extending into the lower fin element.
For support see Liaw, which teaches wherein a first lower fin element continuously extending under the first plurality of nanostructures and the third plurality of nanostructures (see Liaw, Figs.8 and 11 as shown above, ¶ [0040], and ¶ [0045]); and
a fin-cut structure (240A) interposed between the first gate stack and the second gate stack and extending into the lower fin element (see Liaw, Figs.8 and 11 as shown above, ¶ [0040], and ¶ [0045]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chou, Kim, Lee, and Liaw to enable the first lower fin element continuously extending under the first plurality of nanostructures and the third plurality of nanostructures and the fin-cut structure to be interposed between the first gate stack and the second gate stack and extending into the lower fin element as taught by Liaw in order to truncating the p-type fins and n-type fin and reducing a gate pitch between adjacent gate stacks.
Claim(s) 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (U.S. 2023/0380130 A1, hereinafter refer to Chou) in view of Kim et al. (U.S. 2025/0098327 A1, hereinafter refer to Kim) and Lee et al. (U.S. 2023/0189496 A1, hereinafter refer to Lee).
Regarding Claim 10: Chou discloses a semiconductor structure (see Chou, Figs.5-6D as shown above and ¶ [0018]), comprising:
a first cell region (100A) comprising a first transistor including a first channel layer, and a second transistor including a second channel layer, wherein the first transistor and the second transistor share a first gate stack (208A) (see Chou, Figs.5-6D as shown above);
a second cell region (100B) comprising a third transistor including a third channel layer, a fourth transistor including a fourth channel layer, wherein the third transistor and the fourth transistor share a second gate stack (208E), in a horizontal direction that is parallel to a longitudinal direction of the first gate stack (208A) (see Chou, Figs.5-6D as shown above);
a first contact plug (226C) on drain nodes of the first transistor and the second transistor (see Chou, Figs.5-6D as shown above);
a second contact plug (226C) on drain nodes of the third transistor and the fourth transistor (see Chou, Figs.5-6D as shown above).
Chou is silent upon explicitly disclosing wherein a first metal layer over the first contact plug and the second contact plug; and
a second metal layer over the first metal layer, wherein a first line in the second metal layer and the second contact plug are electrically connected in parallel through at least two lines in the first metal layer.
For support see Kim, which teaches wherein a first metal layer (M1) over the first contact plug and the second contact plug (CA) (see Kim, Fig.7A as shown above, ¶ [0056]- ¶ [0059], and ¶ [0071]); and
a second metal layer (M2) over the first metal layer (M1), wherein a first line in the second metal layer (M2) and the second contact plug (CA) are electrically connected in parallel through at least two lines in the first metal layer (M1) (see Kim, Fig.7A as shown above, ¶ [0056]- ¶ [0059], and ¶ [0071]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chou and Kim to enable the first metal layer to be over the first contact plug and the second contact plug and the second metal layer to be over the first metal layer, wherein a first line in the second metal layer and the second contact plug electrically connected in parallel through at least two lines in the first metal layer as taught by Kim in order to electrically connect the source/drain regions SD the second metal layer through the source/drain contacts CA and first metal layer.
The combination of Chou and Kim is silent upon explicitly disclosing wherein a third channel layer is wider than the first channel layer and the fourth channel layer is wider than the second channel layer.
For support see Lee, which teaches wherein a third channel layer (W2) is wider than the first channel layer (W1) and the fourth channel layer (W2) is wider than the second channel layer (W1) (see Lee, Fig.7 as shown above and ¶ [0022]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chou, Kim, and Lee to enable the third channel layer to be wider than the first channel layer and the fourth channel layer to be wider than the second channel layer as taught by Lee in order to provide superior channel electrostatics control.
Regarding Claim 11: Chou as modified teaches a semiconductor structure as set forth in claim 10 as above. The combination of Chou, Kim, and Lee further teaches wherein a first cell height of the first cell region (100A) is equal to a second cell height of the second cell region (100B) (see Chou, Figs.5-6D as shown above).
Regarding Claim 12: Chou as modified teaches a semiconductor structure as set forth in claim 10 as above. The combination of Chou, Kim, and Lee further teaches wherein a first cell height of the first cell region is 1.5 times or twice a second cell height of the second cell region (see Lee, Fig.7 as shown above and ¶ [0033]).
Regarding Claim 13: Chou as modified teaches a semiconductor structure as set forth in claim 10 as above. The combination of Chou, Kim, and Lee further teaches wherein a second line in the second metal layer (M2) is electrically connected in series to the first contact plug (CA) through a line in the first metal layer (M1) (see Kim, Fig.7A as shown above).
Regarding Claim 14: Chou as modified teaches a semiconductor structure as set forth in claim 10 as above. The combination of Chou, Kim, and Lee is silent upon explicitly disclosing wherein the second gate stack is longer than the first gate stack in the horizontal direction.
However, practicing the combination of Chou, Kim, and Lee to modify the Chou’s third channel layer to be wider than the first channel layer and the fourth channel layer to be wider than the second channel layer as taught by Lee necessarily results the Chou’s second gate stack to be longer than the first gate stack in the horizontal direction as now specified in claim 14.
Regarding Claim 15: Chou as modified teaches a semiconductor structure as set forth in claim 10 as above. The combination of Chou, Kim, and Lee further teaches wherein in a plan view, the second contact plug (CA) is confined within an area of the first line of the second metal layer (M2) (see Chou, Figs.5-6D as shown above and see Kim, Fig.7A as shown above).
Conclusion
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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