Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 4-5, 7, 15, and 17 are objected to because of the following informalities:
Claim 4 recites the limitation of “the the” in line 11.
Claim 5 recites the limitation of “the the” in line 4.
Claim 5 recites the limitation of “the the” in line 7.
Claim 15 recites the limitation of “the the” in line 2.
Appropriate correction is required.
Claim 7 recites the limitation “the second n-type nanostructure" in line 4 and “the second p-type nanostructure” in line 7. There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “the second n-type nanostructure" and “the second p-type nanostructure” relates back to “the first n-type nanostructure" in line 3 and “the first p-type nanostructure” in line 6, respectively.
For purpose of compact prosecution, “the second n-type nanostructure" in line 4 and “the second p-type nanostructure” will be treated as if it were “the first n-type nanostructure" and “the first p-type nanostructure”, respectively.
Claim 17 recites the limitation “the first third plurality of nanostructures" in lines 5-6. It is unclear whether “the first third plurality of nanostructures” was intended to relate back to “a first plurality of nanostructures” claim 16, line 2.
For purpose of compact prosecution, “the first third plurality of nanostructures” will be treated as if it were “the first plurality of nanostructures.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10, first recites the limitation “the second metal layer includes a fourth line" in line 15. In lines 17-18, claim 10, recites the limitation “the second metal line is electrically isolated from the second contact plug and the fourth line." It is unclear how “the second metal layer includes a fourth line" electrically isolated from “the fourth line.” There is insufficient antecedent basis for this limitation in the claim.
Claims 11- 15 are rejected as it depends on rejected claim 10.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7, 9, 16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YOU et al. (U.S. 2021/0134837 A1, hereinafter refer to YOU).
Regarding Claim 1: YOU discloses a semiconductor structure (see YOU, Figs.10-13 and 15 as shown below and ¶ [0002]), comprising:
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a first circuit in a first cell region (20 or 22), the first circuit comprising a first n-type nanostructure (114NS) transistor and a first p-type nanostructure (112NS) transistor (see YOU, Figs.10-13 as shown above and ¶ [0036]- ¶ [0039]);
a first contact plug (170) electrically connected to drain nodes of the first n-type nanostructure (114NS) transistor and the first p-type nanostructure (112NS) transistor (see YOU, Figs.10-13 as shown above and ¶ [0063]);
a first metal layer (191/192) over the first contact plug (170) and comprising a first line (192) and a second line (191) electrically connected to the first contact plug (170), wherein the first line (192) and the second line (191) extend lengthwise along a first direction and are spaced apart from each other (see YOU, Figs.10-13 as shown above and ¶ [0078]); and
a second metal layer (210) over the first metal layer (191/192) and comprising a third line (210) electrically connected to both the first line (192) and the second line (191), wherein the third line extends lengthwise along a second direction that is different than the first direction (see YOU, Figs.10-13 as shown above and ¶ [0081]).
Regarding Claim 2: YOU discloses a semiconductor structure as set forth in claim 1 as above. YOU further teachers wherein the third line (210) at least partially overlaps the first contact plug (170) (see YOU, Figs.10-13 as shown above).
Regarding Claim 3: YOU discloses a semiconductor structure as set forth in claim 1 as above. YOU further teachers wherein a first via (196) interposed between the first line (192) and the first contact plug (170) (see YOU, Figs.10-13 as shown above);
a second via (197) interposed between the second line (191) and the first contact plug (170) (see YOU, Figs.10-13 as shown above);
a third via (215) interposed between the first line (192) and the third metal line (210), wherein the third via (215) at least partially overlaps the first via (196) (see YOU, Figs.10-13 as shown above); and
a fourth via (215) interposed between the second line (191) and the third metal line (210), wherein the fourth via (215) at least partially overlaps the second via (197) (see YOU, Figs.10-13 as shown above).
Regarding Claim 7: YOU discloses a semiconductor structure as set forth in claim 1 as above. YOU further teachers wherein the first metal layer further comprises: a Vss power rail (195_1) electrically connected to source nodes of the first n-type nanostructure (114NS) transistor of the first circuit and the second n-type nanostructure (114NS) transistor of the second circuit (see YOU, Figs.10-13 as shown above); and
a Vdd power rail (195_2) electrically connected to source nodes of the first p-type nanostructure (112NS) transistor of the first circuit and the second p-type nanostructure (112NS) transistor of the second circuit (see YOU, Figs.10-13 as shown above).
Regarding Claim 9: YOU discloses a semiconductor structure as set forth in claim 1 as above. YOU further teachers wherein the first metal layer (191/192) further comprises a fourth line (191 or 192) electrically connected to the first contact plug (170) and the third line (210) of the second metal layer (210) (see YOU, Figs.10-13 as shown above).
Regarding Claim 16: YOU discloses a semiconductor structure (see YOU, Figs.10-13 and 15 as shown above and ¶ [0002]), comprising:
a first gate stack (120) wrapping around a first plurality of nanostructures (114NS) and a second plurality of nanostructures (112NS) (see YOU, Figs.10-13 as shown above);
a first source/drain feature (130) and a second source/drain feature (130) adjoining a first side of the first plurality of nanostructures (114NS) and a first side of the second plurality of nanostructures (112NS) (see YOU, Figs.10-13 as shown above), respectively;
a third source/drain feature (130) and a fourth source/drain feature (130) adjoining a second side of the first plurality of nanostructures (114NS) and a second side of the second plurality of nanostructures (112NS) (see YOU, Figs.10-13 as shown above), respectively;
a first contact plug (170) on both the first source/drain feature (130) and the second source/drain feature (130) (see YOU, Figs.10-13 as shown above);
a second contact plug (170) on the third source/drain feature (130) (see YOU, Figs.10-13 as shown above);
a third contact plug (170) on the fourth source/drain feature (130) (see YOU, Figs.10-13 as shown above);
a first via (196) and a second via (197) on the first contact plug (170) (see YOU, Figs.10-13 as shown above);
a third via (196) and a fourth via (197) on the second contact plug (170) and the third contact plug (170), respectively a first metal line (192) and a second metal line (192) on the first via (196) and the second via (196) (see YOU, Figs.10-13 as shown above), respectively;
a third metal line (191) and a fourth metal line (191) on the third via (197) and the fourth via (197), respectively, wherein the first metal line (192), the second metal line (192), the third metal line (191) and the fourth metal line (191) are located on the same plane, and in a plan view, the first metal line (192) and the second metal line (192) are located between the third metal line (191) and the fourth metal line (191) (see YOU, Figs.10-13 as shown above);
a fifth via (215) and a sixth via (215) on the first metal line (192) and the second metal line (192) (see YOU, Figs.10-13 as shown above), respectively; and
a fifth metal line (210) on both the fifth via (215) and the sixth via (215) (see YOU, Figs.10-13 as shown above).
Regarding Claim 20: YOU discloses a semiconductor structure as set forth in claim 16 as above. YOU further teachers wherein a first dielectric isolation structure (106) below the first source/drain feature (130) (see YOU, Figs.10-13 as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over YOU et al. (U.S. 2021/0134837 A1, hereinafter refer to YOU) as applied to claims 1 and 16 above, and further in view of Lee et al. (U.S. 2023/0189496 A1, hereinafter refer to Lee).
Regarding Claim 4: YOU discloses a semiconductor structure as applied to claim 1 above. YOU further teachers wherein a second circuit in a second cell region (20 or 22), the second circuit comprising a second n-type nanostructure (114NS) transistor and a second p-type nanostructure (112NS) transistor (see YOU, Figs.10-13 as shown above and ¶ [0036]- ¶ [0039]); and
a second contact plug (170) electrically connected to drain nodes of the second n-type nanostructure (114NS) transistor and the second p-type nanostructure (112NS) transistor (see YOU, Figs.10-13 as shown above and ¶ [0063]);
wherein: the first n-type nanostructure (114NS) transistor of the first circuit includes a first plurality of nanostructures having a first width in the second direction that is parallel to a longitudinal axis of the first contact plug (170) (see YOU, Figs.10-13 as shown above and ¶ [0038]), and
the second n-type nanostructure (114NS) transistor of the second circuit includes a second plurality of nanostructures having a second width in the the second direction (see YOU, Figs.10-13 as shown above and ¶ [0038])).
YOU is silent upon explicitly disclosing wherein the second width is less than the first width.
For support see Lee, which teaches wherein the second width (W1) is less than the first width (W2) (see Lee, Fig.7 as shown below and ¶ [0022]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of YOU and Lee to enable the second width of YOU to be less than the first width as taught by Lee in order to provide superior channel electrostatics control.
Regarding Claim 5: YOU discloses a semiconductor structure as set forth in claim 4 as above. The combination of YOU and Lee further teachers wheren the second p-type nanostructure (112NS) transistor of the first circuit includes a third plurality of nanostructures having a third width in the the second direction (see YOU, Figs.10-13 as shown above and ¶ [0036]), and
the second p-type nanostructure (112NS) transistor of the second circuit includes a fourth plurality of nanostructures having a fourth width in the the second direction (see YOU, Figs.10-13 as shown above).
You is silent upon explicitly disclosing wherein the fourth width is less than the third width.
For support see Lee, which teaches wherein the fourth width (W1) is less than the third width (W2) (see Lee, Fig.7 as shown above and ¶ [0022]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of YOU and Lee to enable the fourth width of YOU to be less than the third width as taught by Lee in order to provide superior channel electrostatics control.
Regarding Claim 6: YOU discloses a semiconductor structure as set forth in claim 4 as above. The combination of YOU and Lee further teachers wherein a ratio of the first width (W2) to the second width (W1) is in a range from about 1.5 to about 8 (see Lee, Fig.7 as shown above and ¶ [0033]).
Regarding Claim 17: YOU discloses a semiconductor structure as applied to claim 16 above. YOU further teachers wherein a second gate stack (120) wrapping around a third plurality of nanostructures (114NS) and a fourth plurality of nanostructures (112NS), wherein in a horizontal direction that is parallel to a longitudinal direction of the first gate stack (120) (see YOU, Figs.10-13 as shown above);
a fifth source/drain feature (130) and a sixth source/drain feature (130) adjoining the third plurality of nanostructures (114NS) and the fourth plurality of nanostructures (112NS) (see YOU, Figs.10-13 as shown above), respectively; and
a fourth contact plug (170-1) on both the fifth source/drain feature (130) and the sixth source/drain feature (130), wherein in the horizontal direction, the fourth contact plug (170-1) is shorter than the first contact plug (170) (see YOU, Figs.10-13 as shown above).
YOU is silent upon explicitly disclosing wherein a third plurality of nanostructures is narrower than the first third plurality of nanostructures and the fourth plurality of nanostructures is narrower than the second plurality of nanostructures.
For support see Lee, which teaches wherein a third plurality of nanostructures (W1) is narrower than the first third plurality of nanostructures (W2) and the fourth plurality of nanostructures (W1) is narrower than the second plurality of nanostructures (W2) (see Lee, Fig.7 as shown above and ¶ [0022]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of YOU and Lee to enable the third plurality of nanostructures narrower than the first third plurality of nanostructures and the fourth plurality of nanostructures narrower than the second plurality of nanostructures as taught by Lee in order to provide superior channel electrostatics control.
Regarding Claim 18: YOU discloses a semiconductor structure as set forth in claim 17 as above. The combination of YOU and Lee further teachers wherein the first plurality of nanostructures (114NS) and the third plurality of nanostructures (114NS) are located in a p-type well, and the second plurality of nanostructures (112NS) and the fourth plurality of nanostructures (112NS) are located in an n-type well (see YOU, Figs.10-13 as shown above, ¶ [0036], and ¶ [0038]).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over YOU et al. (U.S. 2021/0134837 A1, hereinafter refer to YOU) as applied to claim 1 above, and further in view of Liaw et al. (U.S. 2021/0202498 A1, hereinafter refer to Liaw).
Regarding Claim 8: YOU discloses a semiconductor structure as applied to claim 1 above. YOU further teachers wherein the first cell region abuts the second cell region (see YOU, Figs.10-13 as shown above).
YOU is silent upon explicitly disclosing wherein the semiconductor structure further comprises: a fin-cut structure on a boundary between the first cell region and the second cell region.
For support see Liaw, which teaches wherein the semiconductor structure further comprises: a fin-cut structure (240) on a boundary between the first cell region (Sy-1) and the second cell region (Sy-2) (see Liaw, Figs.8 and 11 as shown below, ¶ [0040], and ¶ [0045]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of YOU and Liaw to enable the semiconductor structure further to comprise a fin-cut structure on a boundary between the first cell region and the second cell region as taught by Liaw in order to truncating the p-type fins and n-type fin and reducing a gate pitch between adjacent gate stacks.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over YOU et al. (U.S. 2021/0134837 A1, hereinafter refer to YOU) and Lee et al. (U.S. 2023/0189496 A1, hereinafter refer to Lee) as applied to claim 17 above, and further in view of Liaw et al. (U.S. 2021/0202498 A1, hereinafter refer to Liaw).
Regarding Claim 19: YOU discloses a semiconductor structure as applied to claim 17 above. The combination of YOU and Lee further teachers wherein a first lower fin element continuously extending under the first plurality of nanostructures (114NS) and the third plurality of nanostructures (114NS) (see YOU, Figs.10-13 as shown above).
The combination of YOU and Lee is silent upon explicitly disclosing wherein a fin-cut structure interposed between the first gate stack and the second gate stack and extending into the lower fin element.
For support see Liaw, which teaches wherein a fin-cut structure (240A) interposed between the first gate stack and the second gate stack and extending into the lower fin element (see Liaw, Figs.8 and 11 as shown above, ¶ [0040], and ¶ [0045]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of YOU, Lee, and Liaw to enable the fin-cut structure to be interposed between the first gate stack and the second gate stack and extending into the lower fin element as taught by Liaw in order to truncating the p-type fins and n-type fin and reducing a gate pitch between adjacent gate stacks.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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