DETAILED ACTION
This Office Action is in response to Applicant’s application 18/631,525 filed on April 10, 2024 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on April 10, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “second middle dielectric layer” of claim 8 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
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Claims 1-2 and 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 2025/0203935 (Reboh) and U.S. 2022/0109046 (Hong).
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Regarding claim 1, Reboh discloses at annotated Figures 4A and 4B a semiconductor structure, comprising:
a bottom transistor, 700 [0049], comprising a plurality of first nanostructures, 12A [0043], and a first gate structure, 76A [0049-50], wrapped around the plurality of first nanostructures, as shown;
a top transistor, 701 [0049], above the bottom transistor, as shown, comprising a plurality of second nanostructures, 12B [0043], and a second gate structure, 76B [0049-50], wrapped around the plurality of second nanostructures, as shown; and
a first middle dielectric layer, 41 [0047], between the first gate structure and the second gate structure, as shown.
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Reboh does not teach a first width of one of the first nanostructures is greater than a second width of one of the second nanostructures and the first middle dielectric layer has a third width, and the third width is larger than the second width.
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Hong is directed to uses of GAA CFET transistors. Regarding claim 1, Hong teaches at annotated Figure 3A and 3C a semiconductor structure, comprising: a bottom transistor, as annotated, comprising a plurality of first nanostructures, 310 [0050], and a first gate structure, 315 [0050], wrapped around the plurality of first nanostructures, as shown; a top transistor, as annotated, above the bottom transistor, as shown, comprising a plurality of second nanostructures, 320 [0050], and a second gate structure, 325 [0050], wrapped around the plurality of second
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nanostructures, as shown, wherein a first width of one of the first nanostructures is greater than a second width of one of the second nanostructures, as shown in Figure 3C and described at [0052]; and a first middle dielectric layer, 330 [0056], between the first nanostructure and the second nanostructure, as shown, wherein the first middle dielectric layer has a third width, and the third width is larger than the second width, as shown in Figure 3C.
At [0049] Hong teaches this configuration of transistors is useful to implement an inverter circuit and at [0067] the smaller width of the upper transistor allows more space for the source/drain contact.
Taken as a whole, the prior art is directed to CFET devices using P and N type GAA transistors. Hong teaches the smaller width of the upper transistor allows more space for the source/drain contact. An artisan would find it desirable to allow more space for a source/drain contact to improve manufacturability of the device.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 where first width of one of the first nanostructures is greater than a second width of one of the second nanostructures and the first middle dielectric layer has a third width, and the third width is larger than the second width, as taught by Hong, to implement an inverter circuit with more room for a source/drain contact, as taught by Hong, and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 2 which depends upon claim 1, Reboh teaches the bottom transistor further comprises a first S/D structure, 62A [0051], the top transistor further comprises a second S/D structure, 62B [0051], and there is a spacer dielectric layer, 61 [0051], between the first S/D structure and the second S/D structure, as shown.
Regarding claim 4 which depends upon claim 1, Hong teaches a first number of the first nanostructures is different from a second number of the second nanostructures at Figure 3A.
Regarding claim 5 which depends upon claim 1, Reboh teaches a first inner spacer layer, 55 [0071], adjacent to the first gate structure, wherein an outer sidewall surface of the first inner spacer layer is aligned with an outer sidewall surface of the first middle dielectric layer, as shown.
Regarding claim 6 which depends upon claim 5, Reboh suggests the first inner spacer layer and the first middle dielectric layer are made of different materials and Examiner notes that it is well known in the art to use different materials for inner spacers and MDI to facilitate the manufacturing process.
Regarding claim 7 which depends upon claim 1, at [0050] Reboh teaches the first gate structure includes a first-type work function layer, and the second gate structure includes a second-type work function layer.
Allowable Subject Matter
Claims 3 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3 the prior art does not teach the device claim 2, wherein a top surface of the spacer dielectric layer is lower than a top surface of the first middle dielectric layer.
Regarding claim 8 the prior art fails to disclose the device of claim 1, further comprising: a second middle dielectric layer between the first gate structure and the second gate structure, wherein the second dielectric layer is in direct contact with the first middle dielectric layer.
Claims 9-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 9 the prior art fails to disclose the device of claim 8 comprising a gate spacer layer adjacent to the second gate structure, wherein the gate spacer layer has an inner sidewall surface in direct contact with the first gate structure; and a first middle dielectric layer between the first gate structure and the second gate structure, wherein a sidewall surface of the first middle dielectric layer extends beyond the inner sidewall surface of the gate spacer layer.
Regarding claim 16, the prior art fails to disclose the method of claim 16 forming a sacrificial layer on the first stack structure; forming a second stack structure on the sacrificial layer; patterning the second stack structure and the sacrificial layer to form a patterned second stack structure and a patterned sacrificial layer; forming a spacer layer on a sidewall surface of the patterned second stack structure and a sidewall surface of the patterned sacrificial layer; patterning the first stack structure by using the patterned second stack structure and the patterned sacrificial layer as a mask to form a patterned first stack structure; forming a dummy gate structure on the patterned first stack structure, the patterned second stack structure and the patterned sacrificial layer; removing the patterned sacrificial layer to form a recess; forming a first middle dielectric layer in the recess; removing the dummy gate structure to form a trench; removing the first semiconductor materials of the patterned first stack structure to form first nanostructures; removing the first semiconductor materials of the patterned second stack structure to form second nanostructures; forming a first gate structure surrounding the first nanostructures; and forming a second gate structure surrounding the second nanostructures, wherein the first middle dielectric layer is between the first gate structure and the second gate structure.
Claims 10-15 and 17-20 depend directly or indirectly on claims 9 or 16 and are allowable on that basis.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893
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