DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of invention I, claims 1-10, in the reply filed on 07/08/2026 is acknowledged. The traversal is on the ground(s) that the identified groups pertain to a generic concept and would not impose serious search and/or examination burden. This is not found persuasive because invention II and invention I are related as process of making and product made. The inventions are distinct as the product as claimed can be made by another and materially different process. Furthermore, there would be a serious search burden because the inventions have acquired different classification; the inventions require a different field of search. See Office Action mailed on 05/18/2026, pages 2 to 3.
The requirement is still deemed proper and is therefore made FINAL.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/08/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2024/0047419) in view of Ravichandran (US 2024/0337799).
Regarding claim 1, Kim discloses, in FIG. 2 and in related text, an electronic package, comprising:
a cladding layer (240) having a first surface (top surface), a second surface (bottom surface) opposing the first surface, and side surfaces adjacent to the first surface and the second surface;
at least one first electronic element (230) embedded in the cladding layer;
a plurality of conductive pillars (250) embedded in the cladding layer;
a circuit structure (310) formed on the first surface of the cladding layer and electrically connected to the plurality of conductive pillars and the at least one first electronic element;
an auxiliary electronic element (320) disposed on and connected to the circuit structure; and
a plurality of second electronic elements (330) disposed on and electrically connected to the circuit structure (see Kim, [0023], [0032], [0036], [0039], [0042], [0044], [0048]).
Kim does not explicitly disclose wherein the plurality of second electronic elements are photonic integrated circuit chips.
Ravichandran teaches wherein the plurality of second electronic elements (510, 512) are photonic integrated circuit chips (see Ravichandran, FIG. 11, [0071]).
Kim and Ravichandran are analogous art because they both are directed to semiconductor device packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim with the features of Ravichandran because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kim to include wherein the plurality of second electronic elements are photonic integrated circuit chips, as taught by Ravichandran, to provide an integrated circuit package assembly including photonic integrated circuit with embedded active and passive circuit elements and devices (see Ravichandran, [0022]).
Regarding claim 2, Kim in view of Ravichandran teaches the package of claim 1.
Kim discloses wherein the at least one first electronic element (230) is bonded and electrically connected to a plurality of conductors (230BP) (see Kim, FIG. 2, [0032]).
Regarding claim 3, Kim in view of Ravichandran teaches the package of claim 2.
Kim discloses wherein the plurality of conductors (230BP) are covered by a protective film (221) and embedded in the cladding layer (240), and the plurality of conductors are electrically connected to the circuit structure (310) (see Kim, FIG. 2, [0028], [0034], [0039], [0065]).
Regarding claim 4, Kim in view of Ravichandran teaches the package of claim 1.
Kim discloses wherein the at least one first electronic element (230) is surrounded by the plurality of conductive pillars (250) (see Kim, FIG. 2, [0035]).
Regarding claim 6, Kim in view of Ravichandran teaches the package of claim 1.
Ravichandran teaches wherein the plurality of second electronic elements (510, 512) protrude from the side surfaces of the cladding layer (molding compounds) (see Ravichandran, FIG. 11, [0072]-[0073]: molding compounds encapsulates lower components), with at least the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1, and to promote attachment of a waveguide fiber to the photonics integrated circuit (see Ravichandran, [0073]).
Regarding claim 7, Kim in view of Ravichandran teaches the package of claim 1.
Kim discloses wherein the plurality of second electronic elements (330) are externally connected to electrical connectors (330BP) (see Kim, FIG. 2, [0042]).
Regarding claim 8, Kim in view of Ravichandran teaches the package of claim 1.
Kim discloses a circuit portion (210) formed on the second surface (bottom surface) of the cladding layer (240) and electrically connected to the plurality of conductive pillars (250) (see Kim, FIG. 2, [0024], [0035]).
Regarding claim 9, Kim in view of Ravichandran teaches the package of claim 8.
Kim discloses a plurality of conductive elements (BP2) formed on the circuit portion (210) (see Kim, [0046]).
Regarding claim 10, Kim in view of Ravichandran teaches the package of claim 1.
Kim discloses a carrier structure (100) disposed on the second surface (bottom surface) of the cladding layer (240) (see Kim, FIG. 2, [0021]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ravichandran, and further in view of Shibata (US 2025/0300063).
Regarding claim 5, Kim in view of Ravichandran teaches the package of claim 1.
Kim discloses wherein the auxiliary electronic element (320) is a semiconductor chip (see Kim, FIG. 2, [0020]).
Kim and Ravichandran do not explicitly disclose or teach wherein the auxiliary electronic element is a switch or a semiconductor chip for heat dissipation. Kim and Ravichandran do not explicitly disclose or teach a semiconductor chip for heat dissipation.
Shibata teaches a semiconductor chip for heat dissipation (with heatsink 20) (see Shibata, FIG. 11, [0196]).
Kim and Shibata are analogous art because they both are directed to semiconductor device packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim with the features of Shibata because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify Kim to include a semiconductor chip for heat dissipation, as taught by Shibata, to further improve heat dissipation of the device (see Shibata, [0143]).
Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Raghunathan (US 2019/0333905) in view of Chen (US 2015/0155203).
Regarding claim 1, Raghunathan discloses, in FIG. 1a and in related text, an electronic package, comprising:
a circuit structure (redistribution layer RDL 115);
an auxiliary electronic element (122) disposed on and connected to the circuit structure; and
a plurality of second electronic elements (105) disposed on and electrically connected to the circuit structure, wherein the plurality of second electronic elements are photonic integrated circuit chips (see Raghunathan, [0040]-[0041], [0044], [0051]).
Raghunathan does not explicitly disclose:
a cladding layer having a first surface, a second surface opposing the first surface, and side surfaces adjacent to the first surface and the second surface;
at least one first electronic element embedded in the cladding layer;
a plurality of conductive pillars embedded in the cladding layer;
a circuit structure formed on the first surface of the cladding layer and electrically connected to the plurality of conductive pillars and the at least one first electronic element.
Chen teaches:
a cladding layer (40) having a first surface (top surface), a second surface (bottom surface) opposing the first surface, and side surfaces adjacent to the first surface and the second surface;
at least one first electronic element (24, 25) embedded in the cladding layer;
a plurality of conductive pillars (28) embedded in the cladding layer;
a circuit structure (redistribution layer RDL 54) formed on the first surface of the cladding layer and electrically connected to the plurality of conductive pillars and the at least one first electronic element (see Chen, FIG. 10, [0010], [0012], [0017], [0020]).
Raghunathan and Chen are analogous art because they both are directed to semiconductor device packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Raghunathan with the features of Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Raghunathan to include a cladding layer having a first surface, a second surface opposing the first surface, and side surfaces adjacent to the first surface and the second surface; at least one first electronic element embedded in the cladding layer; a plurality of conductive pillars embedded in the cladding layer; a circuit structure formed on the first surface of the cladding layer and electrically connected to the plurality of conductive pillars and the at least one first electronic element, as taught by Chen, to provide logic functions in a package-on-package structure with reduced thickness and total area (see Chen, [0009], [0020]).
Regarding claim 5, Raghunathan in view of Chen teaches the package of claim 1.
Raghunathan discloses wherein the auxiliary electronic element (122) is a switch or a semiconductor chip for heat dissipation (see Raghunathan, [0041]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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