DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over eon et al. (US 20230328968 A1, hereinafter Seon) in view of Chiang et al. (US 20240179894 A1, hereinafter Chiang)
With regards to claim 1, Seon discloses a semiconductor device (FIGS. 37-45) comprising:
a substrate (substrate 100) comprising a plurality of active regions (active regions 103) and an isolation region (isolation region 112) between the active regions;
a plurality of bit line structures (bit line 395) disposed on the active regions;
a plurality of spacer structures (at least spacers 460) disposed on sidewalls of the bit line structures;
a buried contact (buried contact 475) disposed between the bit line structures;
a barrier layer (eight spacer 490) disposed above the buried contact and on sidewalls of spacer structures;
a metal silicide layer (metal silicide layer 500) disposed on the buried contact;
a metal nitride layer (at least metal nitride 530/532/535, see Paragraph [0126]) disposed on the metal silicide layer; and
a landing pad (metal pattern 545) disposed on the metal nitride layer. (See FIGS. 37 and 45)
However, while Seon discloses the barrier layer (eight spacer 490) being made of a silicon oxide or a silicon nitride, Seon does not explicitly teach wherein a material of the barrier layer is the same as a material of the metal nitride layer, namely titanium nitride (see Paragraphs [0117]-[0126])
Chaing teaches that silicon nitride and titanium nitride are interchangeable materials for use of their dielectric properties. (Paragraph [0035]: “The cap material 219 may be formed from a nitride material selected for dielectric properties. For example, one or more dielectric and/or resistor nitrides may be selected from …silicon nitride (SiNX, Si3N4)…titanium nitride (TIN, Ti2N….”)
It would have been obvious to one of ordinary skill in the art to modify the device of Seon to have the titanium nitride of Chiang, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that substituting silicon nitride for titanium nitride is merely substituting one known element for another to obtain predictable results, namely modifying insulation properties of the layer.
With regards to claim 2, Seon in view of Chaing teaches the semiconductor device of claim 1.
Seon further teaches wherein a side surface of the buried contact is in contact with the spacer structures. (See FIG. 45)
With regards to claim 3, Seon in view of Chaing teaches the semiconductor device of claim 1.
Seon further teaches wherein the metal silicide layer comprises a lower section and an upper section, the lower section is embedded in the buried contact, and the upper section is protruded from the buried contact. (See FIG. 45, where a lower section of 500 is in the buried contact 475, and an upper portion of 500 is outside 475)
With regards to claim 4, Seon in view of Chaing teaches the semiconductor device of claim 3.
Seon further teaches wherein a side surface of the upper section is in contact with the barrier layer. (See Fig. 45)
With regards to claim 5, Seon in view of Chaing teaches the semiconductor device of claim 3.
Seon further teaches wherein a top surface of the upper section is higher than a top surface of the buried contact. (See FIG. 45)
With regards to claim 6, Seon in view of Chaing teaches the semiconductor device of claim 1.
Seon further teaches wherein a width of the metal silicide layer is less than a width of the buried contact. (See FIG. 45, showing a lesser width)
With regards to claim 7, Seon in view of Chaing teaches the semiconductor device of claim 1.
Seon further teaches wherein a side surface of the metal nitride layer is in contact with the barrier layer, and an interface is present between the metal nitride layer and the barrier layer. (See FIG. 45, showing the contact and the interface)
With regards to claim 8, Seon in view of Chaing teaches the semiconductor device of claim 1.
Seon further teaches wherein the buried contact comprises polysilicon, (Paragraph [0110]: “The lower contact plug layer may include or may be formed of, e.g., doped polysilicon...”) the metal silicide layer is a titanium silicide layer, (Paragraph [0123]: “The second metal silicide layer 900 may include or may be formed of, e.g., cobalt titanium silicide (CoTi.sub.xSi.sub.y), where x and y are real numbers, as the first metal silicide layer as shown in FIG. 5.”) the metal nitride layer is a titanium nitride layer, (Paragraph [0126]: “the eighth barrier layer 532 may include or may be formed of a metal nitride, e.g., titanium nitride…”) and the landing pad comprises tungsten. (Paragraph [0126]: “the third metal layer 540 may include or may be formed of metal, e.g., tungsten, titanium, tantalum, etc.”)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8 have been considered but are moot because the new ground of rejection relies on Chiang to teach the use of the titanium nitride, and thus teaches the features of at least claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Song et al. (US 20240306375 A1) – Memory device with different spacers.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
