DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-8 in the reply filed on 06/29/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seon et al. (US 20230328968 A1, hereinafter Seon)
With regards to claim 1, Seon discloses a semiconductor device (FIGS. 37-45) comprising:
a substrate (substrate 100) comprising a plurality of active regions (active regions 103) and an isolation region (isolation region 112) between the active regions;
a plurality of bit line structures (bit line 395) disposed on the active regions;
a plurality of spacer structures (at least spacers 460) disposed on sidewalls of the bit line structures;
a buried contact (buried contact 475) disposed between the bit line structures;
a barrier layer (eight spacer 490) disposed above the buried contact and on sidewalls of spacer structures;
a metal silicide layer (metal silicide layer 500) disposed on the buried contact;
a metal nitride layer (at least metal nitride 530/532/535, see Paragraph [0126]) disposed on the metal silicide layer; and
a landing pad (metal pattern 545) disposed on the metal nitride layer. (See FIGS. 37 and 45)
With regards to claim 2, Seon discloses the semiconductor device of claim 1, wherein a side surface of the buried contact is in contact with the spacer structures. (See FIG. 45)
With regards to claim 3, Seon discloses the semiconductor device of claim 1, wherein the metal silicide layer comprises a lower section and an upper section, the lower section is embedded in the buried contact, and the upper section is protruded from the buried contact. (See FIG. 45, where a lower section of 500 is in the buried contact 475, and an upper portion of 500 is outside 475)
With regards to claim 4, Seon discloses the semiconductor device of claim 3, wherein a side surface of the upper section is in contact with the barrier layer. (See Fig. 45)
With regards to claim 5, Seon discloses the semiconductor device of claim 3, wherein a top surface of the upper section is higher than a top surface of the buried contact. (See FIG. 45)
With regards to claim 6, Seon discloses the semiconductor device of claim 1, wherein a width of the metal silicide layer is less than a width of the buried contact. (See FIG. 45, showing a lesser width)
With regards to claim 7, Seon discloses the semiconductor device of claim 1, wherein a side surface of the metal nitride layer is in contact with the barrier layer, and an interface is present between the metal nitride layer and the barrier layer. (See FIG. 45, showing the contact and the interface)
With regards to claim 8, Seon discloses the semiconductor device of claim 1, wherein the buried contact comprises polysilicon, (Paragraph [0110]: “The lower contact plug layer may include or may be formed of, e.g., doped polysilicon...”) the metal silicide layer is a titanium silicide layer, (Paragraph [0123]: “The second metal silicide layer 900 may include or may be formed of, e.g., cobalt titanium silicide (CoTi.sub.xSi.sub.y), where x and y are real numbers, as the first metal silicide layer as shown in FIG. 5.”) the metal nitride layer is a titanium nitride layer, (Paragraph [0126]: “the eighth barrier layer 532 may include or may be formed of a metal nitride, e.g., titanium nitride…”) and the landing pad comprises tungsten. (Paragraph [0126]: “the third metal layer 540 may include or may be formed of metal, e.g., tungsten, titanium, tantalum, etc.”)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Song et al. (US 20240306375 A1) – Memory device with different spacers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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