DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8, 9, 13-16, 18, 22, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Shimomura et al. (2009/0117716, hereafter Shimomura) in view of Peidous et al. (2015/0115480, hereafter Peidous) and Honda et al. (2009/0197403, hereafter Honda).
Regarding claim 1, Shimomura discloses A method of preparing a multilayer structure, the method comprising: depositing a semiconductor oxynitride layer (104, Fig. 1B, par. 0070) on a first dielectric layer (103, Fig. 1B, par. 0070) in interfacial contact with a front surface of a first semiconductor substrate (101, Fig. 1B, par. 0063), wherein the first semiconductor substrate comprises two major, generally parallel surfaces (101, Fig. 1B), one of which is the front surface (101 top, Fig. 1B) of the first single crystal semiconductor substrate and the other of which is a back surface (101 bottom, Fig. 1B) of the first single crystal semiconductor substrate, an edge joining the front surface and the back surface of the first single crystal semiconductor substrate (101 left/right, Fig. 1B), a central plane (101 mid, Fig. 1B) between the front surface and the back surface of the first single crystal semiconductor substrate, and a bulk region between the front and back surfaces of the first single crystal semiconductor substrate (Fig. 1B), wherein the semiconductor oxynitride layer is deposited by plasma enhanced chemical vapor deposition (par. 0070), and bonding a second dielectric layer (112, Fig. 1D, par. 0072) in interfacial contact with a front surface of a second single crystal semiconductor substrate (111, Fig. 1C-1D, par. 0071) to the semiconductor oxynitride layer (Fig. 1G, par. 0118), wherein the second single crystal semiconductor substrate comprises two major, generally parallel surfaces (111 top/bottom, Fig. 1C), one of which is the front surface (111 bottom) of the second single crystal semiconductor substrate and the other of which is a back surface (111 top) of the second single crystal semiconductor substrate, an edge (111 left/right) joining the front and back surfaces of the second single crystal semiconductor substrate, a central plane (111 mid) between the front and back surfaces of the second single crystal semiconductor substrate, and a bulk region (111 mid) between the front and back surfaces of the second single crystal semiconductor substrate, to thereby form a bonded structure (par. 0118) comprising the first semiconductor substrate (101), the first dielectric layer (103), the semiconductor oxynitride layer (104), the second dielectric layer (114), and the second single crystal semiconductor substrate (111) (Fig. 1A – 1G).
Shimomura fails to disclose a first single crystal semiconductor substrate and a circumferential edge.
However, Peidous teaches a first single crystal semiconductor substrate and a circumferential edge (par. 0028).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura with Peidous by providing a single crystal semiconductor substrate with a circumferential edge in order to establish a high quality, defect free lattice to minimize electron scattering defects, ensuring optimal charge carrier mobility and stable thermal dissipation.
Shimomura and Peidous fail to disclose wherein, during deposition of the semiconductor oxynitride layer, at least one process parameter is controlled to produce a nitrogen concentration gradient and an oxygen concentration gradient in the semiconductor oxynitride layer.
However, Honda teaches wherein, during deposition of the semiconductor oxynitride layer, at least one process parameter is controlled to produce a nitrogen concentration gradient and an oxygen concentration gradient in the semiconductor oxynitride layer (par. 0052, 0127).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura and Peidous with Honda by providing at least one process parameter producing nitrogen and oxygen gradients in order to balance interfacial quality and dielectric strength while maximizing thermal stability and defect reduction.
Regarding claim 2, Shimomura discloses a method wherein the at least one process parameter comprises a ratio of a nitrogen precursor gas to an oxygen precursor gas (par. 0070).
Regarding claim 3, Shimomura discloses a method wherein the nitrogen precursor gas comprises ammonia (NH3) and the oxygen precursor gas comprises nitrous oxide (N2O) (par. 0070).
Regarding claim 4, Shimomura and Peidous fail to disclose a method wherein the ratio of the nitrogen precursor gas to the oxygen precursor gas is controlled to increase the oxygen concentration in the semiconductor oxynitride layer away from the first dielectric layer.
However, Honda teaches a method wherein the ratio of the nitrogen precursor gas to the oxygen precursor gas is controlled to increase the oxygen concentration in the semiconductor oxynitride layer away from the first dielectric layer (par. 0052).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura and Peidous with Honda by providing an oxygen concentration in the oxynitride layer that is away from the first dielectric layer in order to create a smooth dielectric transition that lowers interfacial strain, reduces charge trapping, and optimizes breakdown strength and parasitic capacitance.
Regarding claim 8, Shimomura discloses a method wherein depositing the semiconductor nitride layer (103) and depositing the semiconductor oxynitride layer (104) are performed continuously using the plasma enhanced chemical vapor deposition (par. 0070).
Regarding claim 9, Shimomura discloses a method further comprising depositing a semiconductor oxide layer (114, Fig. 1G) on the semiconductor oxynitride layer (104, Fig. 1B, 1G).
Regarding claim 13, Shimomura discloses a method wherein the first (101) and second (111) single crystal semiconductor substrates comprise single crystal silicon (par. 0063, 0071).
Regarding claim 14, Shimomura discloses a method semiconductor oxynitride layer comprises silicon oxynitride (104, par. 0070).
Regarding claim 15, Shimomura discloses a method wherein the semiconductor oxynitride layer has a thickness between 500 angstroms and 10,000 angstroms (par. 0069).
Regarding claim 16, Shimomura fails to explicitly disclose a method wherein the first dielectric layer and the second dielectric layer each comprises a material selected from the group consisting of silicon dioxide, silicon oxynitride, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and any combination thereof.
However, Shimomura teaches a method wherein the first dielectric layer (102) and the second dielectric layer (112) each comprises a material selected from the group consisting of silicon dioxide, silicon oxynitride, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and any combination thereof (par. 0065, 0072).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura by providing dielectrics with various possible materials in order to implement high-k dielectric constants for optimized capacitance, minimal leakage, and process compatibility.
Regarding claim 18, Shimomura discloses a method wherein the first dielectric layer comprises a silicate glass selected from the group consisting of phosphosilicate glass, borosilicate glass, borophosphosilicate glass, and any combination thereof (par. 0207).
Regarding claim 22, Shimomura discloses a method further comprising annealing the bonded structure at a temperature and for a duration (par. 0122) sufficient to strengthen the bond between the second dielectric layer (114) and the semiconductor oxynitride layer (104 contained in 102).
Regarding claim 23, Shimomura discloses a method wherein one of the first and second single crystal semiconductor substrates has a cleave plane (113), wherein the method further comprises mechanically cleaving the bonded structure at the cleave plane (Fig. 1G – 1H, par. 0073-0074).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Shimomura in view of Peidous and Honda as applied to claim 1 above, and further in view of Cros et al. (2014/0234602, hereafter Cros).
Regarding claim 5, Shimomura and Peidos, discussed above, fail to disclose a method wherein, during deposition, the at least one process parameter is controlled to produce the nitrogen concentration gradient and the oxygen concentration gradient in the semiconductor oxynitride layer.
However, Honda teaches a method wherein, during deposition, the at least one process parameter is controlled to produce the nitrogen concentration gradient and the oxygen concentration gradient in the semiconductor oxynitride layer (par. 0052, 0127).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura and Peidous with Honda by providing at least one process parameter producing nitrogen and oxygen gradients in order to balance interfacial quality and dielectric strength while maximizing thermal stability and defect reduction.
Shimomura, Peidous, and Honda fail to disclose that a refractive index of the semiconductor oxynitride layer varies in a range between 1.2 and 3.
However, Cros teaches that a refractive index of the semiconductor oxynitride layer varies in a range between 1.2 and 3 (par. 0038, 0055).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura, Peidous, and Honda with Cros by providing an oxynitride layer such that its refractive index is between 1.2 and 3 because this indicates graded film bridging pure silicon dioxide and silicon nitride which enables precise control over optical antireflection and mechanical stress reduction.
Regarding claim 6, Shimomura, Peidous, and Honda fail to disclose a method wherein the refractive index of the semiconductor oxynitride layer varies in a range between 1.4 and 2.
However, Cros teaches a method wherein the refractive index of the semiconductor oxynitride layer varies in a range between 1.4 and 2 (par. 0038, 0055).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura, Peidous, and Honda with Cros by providing an oxynitride layer such that its refractive index is between 1.4 and 2 because this indicates graded film bridging pure silicon dioxide and silicon nitride which enables precise control over optical antireflection and mechanical stress reduction.
Claims 7, 10, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shimomura in view of Peidous and Honda as applied to claim 1 above, and further in view of Yamazaki et al. (2009/0117704, hereafter Yamazaki).
Regarding claim 7, Shimomura discloses a method further comprising depositing the semiconductor oxynitride layer (104, par. 0070) on the semiconductor nitride layer (103) (Fig. 1B).
Shimomura, Peidous, and Honda fail to disclose depositing a semiconductor nitride layer on the first dielectric layer.
However, Yamakazi teaches depositing a semiconductor nitride layer on the first dielectric layer (par. 0064).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura, Peidous, and Honda with Yamazaki by providing a nitride layer on a dielectric layer in order to serve as an effective etch stop or diffusion barrier to protect the structure.
Regarding claim 10, Shimomura, Peidous, and Honda discussed above, fail to disclose a method wherein depositing the semiconductor oxynitride layer and depositing the semiconductor oxide layer are performed continuously using the plasma enhanced chemical vapor deposition.
However, Yamazaki teaches a method wherein depositing the semiconductor oxynitride layer (112, par. 0060) and depositing the semiconductor oxide layer (116, 0108) are performed continuously using the plasma enhanced chemical vapor deposition (Fig. 1D – 1E, par. 0107).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura, Peidous, and Honda with Yamazaki by performing continuous plasma enhanced CVD to deposit the oxynitride and oxide layer in order to prevents atmospheric contamination and native oxide formation between layers while enables smooth compositional transitions and reduced thermal stress.
Regarding claim 11, Shimomura discloses a method further comprising depositing the semiconductor oxynitride layer (104) on the semiconductor nitride layer (103), and depositing a semiconductor oxide layer (114) on the semiconductor oxynitride layer (Fig. 1B – 1G).
Shimomura, Peidous, and Honda fail to disclose depositing a semiconductor nitride layer on the first dielectric layer.
However, Yamakazi teaches depositing a semiconductor nitride layer on the first dielectric layer (par. 0064).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura, Peidous, and Honda with Yamazaki by providing a nitride layer on a dielectric layer in order to serve as an effective etch stop or diffusion barrier to protect the structure.
Regarding claim 12, Shimomura, Peidous, and Honda fail to disclose a method wherein depositing the semiconductor nitride layer, depositing the semiconductor oxynitride layer, and depositing the semiconductor oxide layer are performed continuously using the plasma enhanced chemical vapor deposition.
However, Yamazaki teaches a method wherein depositing the semiconductor nitride layer (112, par. 0064), depositing the semiconductor oxynitride layer (112, par. 0064), and depositing the semiconductor oxide layer (116, par. 0108) are performed continuously using the plasma enhanced chemical vapor deposition (par. 0065, 0108) (Fig. 1D – 1E).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura, Peidous, and Honda with Yamazaki by performing continuous plasma enhanced CVD to deposit the nitride, oxynitride, and oxide layer in order to prevents atmospheric contamination and native oxide formation between layers while enables smooth compositional transitions and reduced thermal stress.
Claims 17 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Shimomura in view of Peidous and Honda as applied to claim 1 above, and further in view of Lin et al. (2017/0084741, hereafter Lin).
Regarding claim 17, Shimomura, Peidous, and Honda discussed above, fail to disclose a method wherein the first dielectric layer comprises a doped oxide.
However, Lin teaches a method wherein the first dielectric layer comprises a doped oxide (par. 0031).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura, Peidous, and Honda with Lin by providing a first dielectric layer that includes a doped oxide in order to improve step coverage and film conformity while acting as intrinsic dopant diffusion barrier.
Regarding claim 19, Shimomura, Peidous, and Honda fail to disclose a method wherein the first dielectric layer comprises a flowable oxide.
However, Lin teaches a method wherein the first dielectric layer comprises a flowable oxide (par. 0030).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura, Peidous, and Honda with Lin by providing a first dielectric layer that includes a flowable oxide in order to smoothly fill high-aspect-ratio, narrow trench geometries without leaving voids before curing.
Regarding claim 20, Shimomura, Peidous, and Honda fail to disclose a method wherein the first dielectric layer comprises a flowable silazane.
However, Lin teaches a method wherein the first dielectric layer comprises a flowable silazane (par. 0030).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura, Peidous, and Honda with Lin by providing a first dielectric layer that includes a flowable silazane because low viscosity liquid like deposition allows it to fill deep trenches without voids.
Regarding claim 21, Shimomura, Peidous, and Honda fail to disclose a method wherein first dielectric layer comprises a flowable silsesquioxane.
However, Lin teaches a method wherein first dielectric layer comprises a flowable silsesquioxane (par. 0030).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimomura, Peidous, and Honda with Lin by providing a first dielectric layer that includes a flowable silsesquioxane because low viscosity liquid like deposition allows it to fill deep trenches without voids.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Han et al. (20150206757), particularly pertaining to silicate glass of dielectric layer.
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/C.M.B./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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