Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 08/06/2026 has been entered. Claims 1 – 17 are canceled. Claims 18 – 20 are elected without traverse. Claims 21 – 37 are newly added.
Election/Restrictions
Newly submitted claims 24 – 37 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
I. Claims 18 – 23, drawn to a method for manufacturing a semiconductor structure, classified in H10D 30/6735.
II. Claim 24 – 30, drawn to a method for manufacturing a semiconductor structure, classified in H10D 62/151.
III. Claims 31 – 37, drawn to a method for manufacturing a semiconductor structure, classified in H10D 64/017.
Inventions I and II are directed to related method. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions have a materially different design. Inventions I requires fins over a substrate; source/drain features in the fin and on opposite sides of the dummy gate structures; a gate structure in the gate trench to wrap around the second semiconductor layers; while invention II requires fins extending in a first direction; source/drain features attached to the second semiconductor layers in the first direction; a first gate structure and a second gate structure on opposite sides of the first dielectric structure in the second direction.
Inventions I and III are directed to related method. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions have a materially different design. Inventions I requires fins over a substrate; source/drain features in the fin and on opposite sides of the dummy gate structures; a gate structure in the gate trench to wrap around the second semiconductor layers; the gate structure comprises a mortise end portion matching the tenon end portion of the dielectric structure; while invention III requires fins extending in a first direction; source/drain features electrically connected to the second semiconductor layers; a dielectric structure between the second dummy gate structure and the third dummy gate structure; the dielectric structure comprises end portions embedded in the first gate structure and the second gate structure.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 24 – 30, 31 – 37 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Independent Claim 18, line 7, recites: “ different form the first direction ”. However, based on the context in claim 18, it should be “ different from the first direction ” . Please clarify it. For examination purpose, examiner is assuming this section in claim 18 is as suggested above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18 – 23 are rejected under 35 U.S.C. 103 as being unpatentable over Lin ( Pub. No. 20220173225 A1 ), hereinafter Lin, in view of Lin2 (Pub. No. 20170345820 A1), hereinafter Lin2.
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Regarding Independent Claim 18 (Currently Amended), Lin teaches a method for manufacturing a semiconductor structure, comprising:
forming fins ( Lin, FIG. 20, 24, 114, 114’; [0017], semiconductor strips 24; [0020], protruding semiconductor fins 24′; [0053], two stacked layers 114 and 114′ are formed ) over a substrate ( Lin, FIG. 20, 20; [0017], substrate 20 ), wherein each of the fins ( Lin, FIG. 20, 24, 114, 114’ ) comprises first semiconductor layers and second semiconductor layers alternating stacked ( Lin, FIG. 20, 114, 114’, 110, 112; [0053], Each of stacked layers 114 and 114′ includes channel layers 110 and sacrificial films 112 );
forming a dummy gate ( Lin, FIG. 7C, FIG. 20, 30, 30A, 30B; [0022], dummy gate stacks 30; [0028], The long dummy gate stack 30 is thus cut into two discrete portions 30A and 30B ) structure extending in a first direction and over the fins ( Lin, FIG. 20, 24, 114, 114’ );
forming source/drain ( Lin, FIG. 4, FIG. 5A, FIG. 7C, 42; [0025], epitaxy regions (source/drain regions) 42 are formed by selectively growing a semiconductor material from recesses 40, resulting in the structure in FIG. 5A ) features in the fin ( Lin, FIG. 4, FIG. 5A, FIG. 7C, 24, 40, 42 ) and on opposite sides of the dummy gate ( Lin, FIG. 4, FIG. 5A, FIG. 7C, FIG. 20, 30, 30A, 30B ) structures in a second direction ( Lin, FIG. 4, FIG. 5A, FIG. 7, along fin direction ) different from the first direction ( Lin, FIG. 4, FIG. 5A, FIG. 7, along gate direction );
removing portions of the dummy gate ( Lin, FIG. 7C, FIG. 20, 30, 30A, 30B ) structure and the fins ( Lin, FIG. 7A, FIG. 7B, FIG. 14A, FIG. 14B, 50, 22, 25, [0028], [0049], openings 50 ) to form a trench ( Lin, FIG. 7A, FIG. 7B, FIG. 7C, 50; [0028], Referring to FIG. 7A, a dummy-gate cutting process is performed by etching dummy gate stacks 30 to form openings 50 );
forming a dielectric ( Lin, FIG. 8A, 52, 52-1, 52-2; [0030], openings 50 are filled by layers/regions 52-1 and 52-2, which form gate isolation regions 52, as shown in FIG. 8A ) structure in the trench ( Lin, FIG. 7A, FIG. 7B, FIG. 7C, 50 );
removing the dummy gate structure ( Lin, FIG. 9A, FIG. 9B, 30A, 30B; [0034], Dummy gate stacks 30A and 30B are then removed through etching ), the first semiconductor layers ( Lin, FIG. 20, FIG. 22, 112; [0056], sacrificial films 112 are removed), and portions of the dielectric structure ( Lin, FIG. 10, 52-1; [0035], a first etching process 56 is performed to remove the outer sidewall portions of dielectric layer 52-1 ) to form a gate trench ( Lin, FIG. 9A, FIG. 22, 54A, 54B; [0034], Openings 54A and 54B are formed in the space left by the removed dummy gate electrodes 34 (and possibly dummy gate dielectrics 32); [0055], Dummy gate stacks 30A and 30B are then removed, resulting in trenches 54A and 54B, as shown in FIG. 22 ), wherein the dielectric ( Lin, FIG. 8A, 52, 52-1, 52-2 ) structure comprises a end portion; and
forming a gate structure ( Lin, FIG. 23, 66A, 66B, 64, 62; [0045], Replacement gate stacks 66A and 66B include gate dielectrics 62 and gate electrodes 64 ) in the gate trench ( Lin, FIG. 9A, FIG. 22, 54A, 54B ) to wrap around ( Lin, [0056], sacrificial films 112 are removed, followed by the formation of replacement gates 66A and 66B, which includes gate dielectrics 62 encircling channel layers 110, and gate electrodes 64 filling the remaining spaces between channel layers 110. GAA transistors 68A′ and 68B′ are thus formed ) the second semiconductor layers ( Lin, FIG. 20, 110 ), wherein the gate structure ( Lin, FIG. 23, 66A, 66B, 64, 62 ) comprises a end portion matching the end portion of the dielectric ( Lin, FIG. 8A, 52, 52-1, 52-2 ) structure.
Lin does not explicitly disclose:
wherein the dielectric structure comprises a tenon end portion;
wherein the gate structure comprises a mortise end portion matching the tenon end portion of the dielectric structure.
However, Lin2 teaches:
wherein the dielectric ( Lin2, FIG. 9A, FIG. 9B, 50’; [0027], inner dielectric region 50′ ) structure comprises a tenon end portion;
wherein the gate ( Lin2, FIG. 9A, FIG. 9B, 58A, 58B; [0035], replacement gate stacks 58A and 58B; [0039], both replacement gates 58A and 58B abut the gate isolation plug 52 ) structure comprises a mortise end portion matching the tenon end portion of the dielectric ( Lin2, FIG. 9A, FIG. 9B, 50’ )structure.
Lin and Lin2 are both considered to be analogous to the claimed invention because they are forming the dummy gate cutting process and structure. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin ( dielectric structure ( FIG. 8A, 52, 52-1, 52-2 ) and gate structure ( FIG. 23, 66A, 66B, 64, 62 ) ), to incorporate the teachings of Lin2 ( dielectric structure ( FIG. 9A, FIG. 9B, 50’ ) and gate structure ( FIG. 9A, FIG. 9B, 58A, 58B ) ), to implement that dielectric structure comprises a tenon end portion, and gate structure comprises a mortise end portion matching the tenon end portion of the dielectric structure. Doing so would make gate isolation plug to be thinner, gate stack is longer, and therefore the partial landing will at least be reduced, or substantially eliminated ( Lin2, [0046] ).
Regarding Claim 19 (Original), Lin and Lin2 teach the method as claimed in claim 18, on which this claim is dependent, Lin further teaches: further comprising:
conformally forming a liner layer ( Lin, FIG. 8B-1, 52-1; [0031], as shown in FIG. 8B-1, dielectric layer 52-1 is formed using a conformal deposition method … dielectric layer 52-1 is formed using Atomic Layer Deposition (ALD) ) in the trench ( Lin, FIG. 7B, FIG. 8B-1, 50 );
forming the dielectric structure ( Lin, FIG. 8B-2, 52-2; [0031], Dielectric layer/region 52-2 fills the remaining space of opening 50 (FIG. 7A) unfilled by dielectric layer 52-1 ) over the liner layer ( Lin, FIG. 8B-1, 52-1 ) in the trench ( Lin, FIG. 7B, FIG. 8B-2, 50 ); and
removing a portion of the liner layer ( Lin, FIG. 10, 52-1 ) to form the gate trench ( Lin, FIG. 10, 54A, 54B ).
Regarding Claim 20 (Currently Amended), Lin and Lin2 teach the method as claimed in claim 18, on which this claim is dependent, Lin and Lin2 further teach: further comprising:
forming gate spacers ( Lin, FIG. 3, 38; [0023], gate spacers 38 are formed on the sidewalls of dummy gate stacks 30 ) on opposite sides of the dummy gate structure ( Lin, FIG. 3, 30; [0022], Dummy gate stacks 30 may include dummy gate dielectrics 32 and dummy gate electrodes 34 );
removing portions of the gate spacers to form the trench ( Lin, FIG. 7A, FIG. 7B, 50 ); and
forming the dielectric ( Lin2, FIG. 9A, FIG. 9B, 48’, 50’ ) structure between the gate spacers ( Lin2, FIG. 9A, FIG. 9B, 34A, 34B ), wherein a width of the tenon end portion ( Lin2, FIG. 9A, FIG. 9B, 50’ ) of the dielectric structure in the second direction is less than a width of a middle portion ( Lin2, FIG. 9A, FIG. 9B, 48’, 50’ ) of the dielectric structure in the second direction.
Regarding Claim 21 (New), Lin and Lin2 teach the method as claimed in claim 18, on which this claim is dependent, Lin2 further teaches: further comprising:
wherein the tenon end portion ( Lin2, FIG. 9A, FIG. 9B, 50’ ) of the dielectric structure has a funnel shape ( Lin2, FIG. 9A, FIG. 9B, 50’; [0041], dielectric region 50′ also has curved sidewalls 51 ) in a top view.
Regarding Claim 22 (New), Lin and Lin2 teach the method as claimed in claim 18, on which this claim is dependent, Lin2 further teaches: further comprising:
wherein the tenon end portion of the dielectric structure has a spike shape ( Lin, Lin2, FIG. 9A, FIG. 9B, 50’; [0041], Curved sidewalls 51 have center portions protruding more toward replacement gate 58A/58B, and the protruding distance R2 (FIG. 9B) may be greater than about 5 Å. Protruding distance R2 may also be in the range between about 5 Å and about 5 nm) in a top view.
Regarding Claim 23 (New), Lin and Lin2 teach the method as claimed in claim 18, on which this claim is dependent, Lin further teaches: further comprising:
wherein the dielectric structure ( Lin, FIG. 8A, 52, 52-1, 52-2 ) has a void ( Lin, [0030], dielectric layers 52-1 and 52-2 are formed of a same material such as silicon oxide, but have different porosity values and hence different density values; [0040], dielectric layer 52-2 being more porous than dielectric layer ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/BRADLEY SMITH/Primary Examiner, Art Unit 2817
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