DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-8 and 17-20) in the reply filed on July 01st, 2026 is acknowledged. Non-elected claims 9-16 have been withdrawn from further consideration by the Applicant.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tolle et al. (U.S. Pub. 2023/0029344).
In re claim 1, Tolle discloses a three-dimensional semiconductor device 200a, comprising a substrate 102 (see paragraph [0021] and fig. 2A); and a monocrystalline semiconductor layer stack (204a-204e), comprising at least one monocrystalline semiconductor layer (204a-204e), separated from, and disposed over a main surface of the substrate 102 (see paragraph [0029] and fig. 2A); and a plurality of epitaxial heterostructures (202a-202e), integrally grown from the at least one monocrystalline semiconductor layer (204a-204e) (see paragraph [0039] and fig. 2A), wherein a first epitaxial heterostructure 202a is disposed on a lower surface of the at least one monocrystalline semiconductor layer 204a, facing the substrate 102, and wherein a second epitaxial heterostructure 202b is disposed on an upper surface of the monocrystalline semiconductor layer 204a, opposite the lower surface (see paragraphs [0029], [0030] and fig. 2A).
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In re claim 2, as applied to claim 1 above, Tolle discloses wherein the monocrystalline semiconductor layer stack comprises a plurality of monocrystalline semiconductor layers (204a-204e), mutually separated from one another along a first direction within a vertical stack, wherein a plurality of heteroepitaxial regions are arranged in alternating fashion with the plurality of monocrystalline semiconductor layers (204a-204e), wherein a given heteroepitaxial region of the plurality of heteroepitaxial regions comprises a crystalline semiconductor/semiconductor alloy stack, wherein the given heteroepitaxial region comprises an upper epitaxial heterostructure 202c, integrally grown from a first monocrystalline semiconductor layer 204b of the plurality of monocrystalline semiconductor layers (204a-e), and wherein the given heteroepitaxial region comprises a lower epitaxial heterostructure 202a, integrally grown from a second monocrystalline semiconductor layer 204a of the plurality of monocrystalline semiconductor layers (204a-204e), the second monocrystalline semiconductor layer 204a being disposed immediately subjacent the first monocrystalline semiconductor layer 204b (see paragraphs [0029], [0030] and fig. 2A).
In re claim 3, as applied to claim 1 above, Tolle discloses wherein the substrate comprises monocrystalline silicon having a first main surface parallel to a (100) crystallographic plane (see paragraph [0027]), wherein the at least one monocrystalline semiconductor layer (204a-204e) comprises silicon (see paragraph [0029] and fig. 2A), and wherein the first epitaxial heterostructure 202a and the second epitaxial heterostructure 202b comprise a Si/SiGe structure (see paragraph [0029] and fig. 2A).
In re claim 4, as applied to claim 1 above, Tolle discloses wherein the three-dimensional semiconductor device further comprising a plurality of vertical support structures 708, extending along a first direction, perpendicularly to a main plane of the substrate, and spaced from one another along a second direction, perpendicular to the first direction, the plurality of vertical support structures connecting the at least one monocrystalline semiconductor layer (204a-204e) to the substrate 102; and a plurality of vertical fill structures 702, extending along the first direction, spaced from one another along the second direction, wherein the plurality of vertical support structures and the plurality of vertical fill structures separate the at least one monocrystalline semiconductor layer (204a-204e) into a three-dimensional array of monocrystalline device regions (see paragraph [0056] and fig. 7).
In re claim 5, as applied to claim 4 above, Tolle discloses wherein the plurality of vertical fill structures comprise an outer layer 704 of epitaxial silicon and an inner layer of silicon nitride (see paragraph [0056] and fig. 7).
In re claim 6, as applied to claim 4 above, Tolle discloses wherein the plurality of vertical fill structures 702 and the plurality of vertical support structures 708 are arranged in a surface pattern that defines a plurality of semiconductor device areas (see paragraph [0056] and fig. 7).
In re claim 7, as applied to claim 6 above, Tolle discloses wherein the surface pattern defines a plurality of rectangles, wherein the plurality of vertical support structures 708 are arranged along a first edge of a given rectangle, and wherein the plurality of vertical fill structures 702 are arranged along a second edge, a third edge, and a fourth edge of the given rectangle (see paragraph [0056] and fig. 7).
In re claim 8, as applied to claim 1 above, Tolle discloses wherein the plurality of epitaxial heterostructures (202a-202e) form a three-dimensional dynamic random access memory (see paragraph [0028] and figs. 2A-2B).
In re claim 17, discloses a three-dimensional memory device, comprising a silicon substrate 102 (see paragraph [0021] and fig. 2A); a monocrystalline semiconductor layer stack, comprising a plurality of monocrystalline silicon layers (204a-204e), disposed over a main surface of the silicon substrate 102 (see paragraph [0029] and fig. 2A), and separated from one another; and a plurality of epitaxial heterostructures (202a-202e), integrally grown from the plurality of monocrystalline silicon layers (204a-204e), wherein a first epitaxial heterostructure 202a is disposed on a lower surface of a given monocrystalline silicon layer 204a, and wherein a second epitaxial heterostructure 202b is disposed on an upper surface of the monocrystalline silicon layer 204a, opposite the lower surface (see paragraphs [0029], [0030] and fig. 2A).
In re claim 20, as applied to claim 17 above, Tolle discloses wherein the plurality of monocrystalline silicon layers (204a-204e) comprise up to five layers (see paragraph [0029] and fig. 2A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tolle et al. (U.S. Pub. 2023/0029344).
In re claim 18, as applied to claim 17 above, Tolle discloses wherein the plurality of epitaxial heterostructures (202a-202e) comprise a Si/SiGe memory stack, the Si/SiGe memory stack having two or four layers (see paragraph [0029] and fig. 2A) but is silent to wherein a given heterostructure of the plurality of epitaxial heterostructures comprises up to 32 Si/SiGe memory stacks.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to form the given heterostructures of the plurality of epitaxial heterostructures comprises up to 32 Si/SiGe memory stacks in order to increase the device integration and improve performance.
In re claim 19, as applied to claim 17 above, Tolle is silent to wherein the plurality of monocrystalline silicon layers individually comprise a thickness of 1 mm to 5 mm.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to optimize the thickness range of the plurality of monocrystalline silicon layers individually to be in a thickness range of about 1 mm to 5 mm during routine experimentation since where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See in re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (U.S. Pub. 2017/0047452) discloses a semiconductor device including, inter-alia, a plurality of sacrificial layers (1221,1222,1223) alternating with a plurality of channel materials (1241,1242,1243) on a substrate 110 (see paragraph [0013] and fig. 1).
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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