DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-2, 6-14 and 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7-9 and 12-20 of U.S. Patent No. 11,024,671. Although the claims at issue are not identical, they are not patentably distinct from each other for the following reasons.
Instant application
Reference Patent (11,024,671)
Difference
Claim 1
1. A method, comprising:
forming a dielectric fin over a substrate;
forming a memory cell disposed along and directly contacting a flat surface of a first sidewall of the dielectric fin, wherein the memory cell comprises:
a first conductor layer,
a resistive material layer and
a second conductor layer, wherein each of the first conductor layer, the resistive material layer and the second conductor layer directly contact the first sidewall; and
forming a capping layer disposed along and directly contacting each of the first conductor layer, the resistive material layer and the second conductor layer such that the memory cell is disposed directly between the capping layer and the dielectric fin.
Claim 6
6. A method of making a memory device, comprising:
forming a dielectric fin over a substrate;
forming a first conductor layer over the substrate and directly contacting a first sidewall of the dielectric fin;
forming a selector layer over the first conductor layer and directly contacting the first sidewall;
forming a resistive material layer over the selector layer and directly contacting the first sidewall; and
forming a second-conductor layer over the resistive material layer and directly contacting the first sidewall; and
forming a capping layer disposed along and directly contacting each of the first conductor layer,
All limitations of claim 1 are disclosed in claim 6 of the reference patent, except for the dielectric fin including a flat surface.
The arrangement of the memory cell, capping layer and dielectric fin is implicitly disclosed in claim 6 of the reference patent.
Claim 2
The method of claim 1, wherein the resistive material layer presents a variable resistance value.
Claim 9
The method of claim 6, wherein the resistive material layer presents a variable resistance value.
Substantially equal
Claim 6
The memory device of claim 1, wherein a lower boundary of the first conductor layer is in contact with a top boundary of the substrate.
Claim 12
The memory device of claim 11, wherein a lower boundary of the first conductor layer is in contact with a top boundary of the substrate.
Substantially equal
Claim 7
The memory device of claim 1, wherein an upper boundary of the first conductor layer, lower and upper boundaries of the resistive material layer, and a lower boundary of the second conductor layer are
each tilted away from the first sidewall of the dielectric fin by an angle less than 90 degrees.
Claims 7 and 13
The method of claim 6, wherein the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer each comprises upper and lower boundaries, and at least one of the upper and lower boundaries of each layer is tilted away from the first sidewall of the dielectric fin by an angle.
8. The method of claim 7, wherein the angle is less than about 90 degrees.
Substantially equal
Claim 8
A method, comprising:
forming a plurality of dielectric fins formed over a substrate; and
forming a plurality of memory cells disposed along respective sidewalls of the plurality of dielectric fins, each memory cells comprising:
a first conductor layer, a resistive material layer, and a second conductor layer, wherein each of the first conductor layer, the resistive material layer and the second conductor layer of each memory cell directly contacts a respective flat surface of a respective sidewall of a respective dielectric fin; and
forming a capping layer disposed along and directly contacting each of the first conductor layer, the resistive material layer, and the second conductor layer
such that the at least one memory cell is disposed directly between the capping layer and a respective dielectric fin of the plurality of dielectric fins.
Claim 14
A method of making a memory device, the method comprising:
forming a plurality of dielectric fins over a substrate; and
forming a plurality of memory cells disposed along respective sidewalls of the plurality of dielectric fins, each memory cells comprising:
a first conductor layer,
forming a capping layer disposed along and directly contacting each of the first conductor layer,
Claim 8 removes the requirement for a selector layer, and adds a flat surface to the dielectric fin.
Claim 9
The method of claim 8, wherein the resistive material layer presents a variable resistance value.
Claim 16
The method of claim 14, wherein the resistive material layer presents a variable resistance value.
Claim 10
The method of claim 8, further comprising forming a selector layer between the first conductive layer and the resistive material layer of each memory cell.
Claim 14
…each memory cells comprising:
…a selector layer…,forming a capping layer disposed along and directly contacting…the selector layer…
Substantially equal
Claim 11
The method of claim 10, further comprising, for each memory cell, forming a third conductor layer, disposed between the first and second conductor layer, wherein the third conductor layer extends along one of the sidewalls of the plurality of dielectric fins.
Claim 17
The method of claim 14, further comprising: forming a third conductor layer for each memory cell, wherein the third conductor layer is disposed between the first and second conductor layers and extends along one of the sidewalls of the plurality of dielectric fins.
Substantially equal
Claim 12
The method of claim 11, wherein the selector layer is disposed between the first and third conductor layers and the resistive material layer is disposed between the third and second conductor layers.
Claim 17
The method of claim 14, wherein the selector layer is disposed between the first and third conductor layers and the resistive material layer is disposed between the third and second conductor layers.
Substantially equal
Claim 13
The method of claim 8, wherein the lower boundary of the first conductor layer is in contact with a top boundary of the substrate.
Claim 19
The method of claim 18, wherein the lower boundary of the first conductor layer is in contact with a top boundary of the substrate.
Substantially equal
Claim 14
The method of claim 8, wherein an upper boundary of the first conductor layer, lower and upper boundaries of the resistive material layer, and a lower boundary of the second conductor layer are each tilted away from the respective sidewall of the respective dielectric fin by an angle less than 90 degrees.
Claims 8 and 20
The method of claim 19, wherein the upper boundary of the first conductor layer, the lower and upper boundaries of the selector layer, the lower and upper boundaries of the third conductor layer, the lower and upper boundaries of the resistive material layer, and the lower boundary of the second conductor layer are each tilted away from the one of the sidewalls of the plurality of dielectric fins by the angle.
Claim 20 of the reference patent discloses a memory cell tilted at an angle, claim 8 of the reference patent discloses a tilt angle of less than 90 degrees.
Claim 16
A method, comprising:
forming a dielectric fin over a substrate, the dielectric fin having a first side surface and a second side surface opposite the first side surface;
forming a first memory cell disposed along and directly contacting a first flat surface of the first side surface of the dielectric fin, the first memory cell comprising: a first lower conductor layer, a first selector layer, a first resistive material layer, and a first upper conductor layer, wherein each of the first lower conductor layer, the first selector layer, the first resistive material layer, and the first upper conductor layer directly contact the first flat surface of the first side surface, wherein lower and upper boundaries of the first selector layer are each tilted away from the first flat surface by an angle, wherein the angle is less than 90 degrees; and
forming a second memory cell disposed along and directly contacting a second flat surface of the second side surface of the dielectric fin, the second memory cell comprising: a second lower conductor layer, a second selector layer, a second resistive material layer, and a second upper conductor layer, wherein each of the second lower conductor layer, the second selector layer, the second resistive material layer, and the second upper conductor layer directly contact the second flat surface of the second side surface; and
forming a capping layer disposed along and directly contacting each of the first lower conductor layer, the selector layer, the resistive material layer, and the first upper conductor layer such that the first memory cell is disposed directly between the capping layer and the dielectric fin.
Claim 1
A method, comprising:
forming a dielectric fin over a substrate;
depositing a first conductor material over the dielectric fin and the substrate;
etching the first conductor material thereby forming a lower conductor layer that has its upper boundary tilted away from a sidewall of the dielectric fin by a first angle;
depositing a selector material over the lower conductor layer, the dielectric fin and the substrate;
etching the selector material thereby forming a selector layer that has its lower and upper boundaries both tilted away from a sidewall of the dielectric fin by a second angle;
depositing a second conductor material over the selector layer, the dielectric fin and the substrate;
etching the second conductor material thereby forming an intermediate conductor layer that has its lower and upper boundaries both tilted away from a sidewall of the dielectric fin by a third angle;
depositing a resistive material over the intermediate conductor layer, the dielectric fin and the substrate;
etching the resistive material thereby forming a resistive material layer that has its upper and lower boundaries both tilted away from the sidewall of the dielectric fin by a fourth angle;
depositing a third conductor material over the resistive material layer, the dielectric fin and the substrate;
etching the third conductor material thereby forming an upper conductor material layer that has its upper and lower boundaries both tilted away from the sidewall of the dielectric fin by a fifth angle; and
depositing a capping layer on at least one sidewall of the first conductor material, the selector material, the second conductor material, the selector material, the resistive material, and the third conductor material surrounding the dielectric fin.
Claim 16 adds the flat surface of the dielectric fin, and more broadly recites method of claims 1 and 14 of the reference patent, removing the features of etching and depositing.
Claim 16 further adds a second resistive layer, which is implicitly disclosed in the plurality of memory cells in claim 14 of the reference patent.
Claim 17
The method of claim 16, wherein the first and second resistive material layers each presents a variable resistance value.
Claim 16
The method of claim 14, wherein the resistive material layer presents a variable resistance value.
Substantially equal
Claim 18
The method of claim 16, wherein the first and second lower conductor layers, the second selector layer, the first and second resistive material layers, and the first and second upper conductor layers each comprises upper and lower boundaries, and at least one of the upper and lower boundaries of each layer is tilted away from the first and second side surfaces, respectively, of the dielectric fin by the angle.
Claim 15
The method of claim 14, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer of each memory cell each includes upper and lower boundaries, and at least one of the upper and lower boundaries of each layer is tilted away from a respective sidewall of one of the plurality of dielectric fins by an angle.
Substantially equal
Although not identical in terminology, the claims of the instant application listed above are disclosed in the reference patent, including a sidewall of a dielectric fin. The additional feature of the dielectric fin including a flat surface is not patentably distinct, as dielectric fins with flat surfaces are well-known in the field of semiconductor manufacturing, and is nothing more than a change in shape.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the double patenting rejection(s) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating:
“forming a dielectric fin over a substrate;
forming a memory cell disposed along and directly contacting a flat surface of a first sidewall of the dielectric fin, wherein the memory cell comprises: a first conductor layer, a resistive material layer and a second conductor layer, wherein each of the first conductor layer, the resistive material layer and the second conductor layer directly contact the first sidewall; and
forming a capping layer disposed along and directly contacting each of the first conductor layer, the resistive material layer and the second conductor layer such that the memory cell is disposed directly between the capping layer and the dielectric fin” as recited in claim 1.
Song et al. (PG Pub. No. US 2018/0375023 A1) teaches a memory device (figs. 5A-5B), comprising a memory cell (P2) disposed along and directly contacting a first sidewall of a dielectric fin (fig. 5A: at least a portion of P2 disposed along and contacting sidewall of 122), the memory cell comprising:
a first conductor layer (240), a selector layer (154), a resistive material layer (230), and a second-conductor layer (220), and
a capping layer (216A) disposed along and directly contacting each of the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer along a second sidewall of the memory cell opposite the first sidewall of the dielectric fin (fig. 5A: 240, 154, 230 and 220 each contact second sidewall of P2 opposite 122),
wherein the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer each comprises upper and lower boundaries, and at least one of the upper and lower boundaries of each layer is tilted away from the first sidewall of the dielectric fin by an angle (upper boundary of 230 tilted with respect to sidewall of 122).
However, Song does not teach a method of forming the first conductor layer includes forming each of the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer tilted away from a sidewall of a dielectric fin.
Ikarashi et al. (PG Pub. No. US 2010/0135068 A1) teaches a memory cell MC including a stack of tilted layers (fig. 9: 1), but is silent to the layers including conductor, selector, and resistive layers contacting a sidewall of a dielectric fin.
Seong et al. (PG Pub. No. US 2019/0305044 A1) teaches a memory cell (134A) including a variable resistance layer (132A), the memory cell tilted away from a first sidewall of a dielectric fin (150) by an angle (fig. 6). However, Seong does not teach each of a first conductor layer, a selector layer, the resistive material layer, and a second conductor layer comprise upper and lower boundaries tilted by the angle.
In light of these limitations in the claims (see the Applicant's fig. 2N & ¶ 0011), the previously applied references do not anticipate or obviate the claimed invention as in the context of the claims.
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818
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