DETAILED ACTION
This Office Action is in response to RCE filed March 5, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 2 is objected to because of the following informalities: “that” should be replaced with “a material” on lines 5 and 6. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2 and 7 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Eshita et al. (US 5,057,880) An alternate interpretation is employed in current Office Action.
Regarding claims 1, 2 and 7, Eshita et al. disclose a semiconductor device (Fig. 6), comprising: a substrate (31) (col. 3, line 67); a nucleation layer (32a) (col. 4, line 56), because the limitation “nucleation” is directed to a product by process limitation and/or an intended use of a layer on which a layer is or layers are subsequently deposited, disposed on the substrate; a buffer layer (composite layer including 33A) (col. 4, line 64) disposed on the nucleation layer, because (a) the limitation “buffer” is also directed to a product by process limitation and/or an intended use of a layer on which a layer is or layers are subsequently deposited, and (b) the preposition “on” does not necessarily suggest “directly on”, the buffer layer comprising: a superlattice layer (33A), comprising a first material (material corresponding to x) and a second material (material corresponding to y) alternately arranged in a periodically ordered relation in a horizontal direction; a third material layer (topmost sublayer of strained superlattice layer 23’) (col. 4, line 58, and col. 2, line 20) disposed on top surfaces of the first material and the second material of the superlattice layer, because when the semiconductor device shown in Fig. 6 of Eshita et al. is viewed upside down, the top surfaces of the first and second material of the superlattice would be the bottommost surfaces of the first and second material layer of the superlattice layer 33A shown in Fig. 6, on which the third material layer, which is the topmost sublayer of strained superlattice layer 23’, is disposed, wherein the third material layer comprises a single material composition (topmost sublayer of strained superlattice layer 23’) continuously extending directly over all of the top surfaces of the first material and the second material of the superlattice layer when the semiconductor device shown in Fig. 6 of Eshita et al. is viewed upside down; a fourth material layer (second topmost sublayer of strained superlattice layer 23’), stacked in sequence with the third material layer in a vertical direction (upside down direction of Fig. 6), an active layer (34) (col. 3, lines 56-57) disposed on the buffer layer; and a gate electrode (35) (col. 6, line 28) disposed on the active layer (claim 1), further comprising a plurality of fifth material layers (some sublayers of strained superlattice layer 23’) and a plurality of sixth material layers (some sublayers of strained superlattice layer 23’) alternately arranged in a periodically ordered relation in the vertical direction on the fourth material layer, wherein each of the fifth material layers comprises a same material as that of the third material layer (topmost sublayer of strained superlattice layer 23’), and each of the sixth material layers comprises a same material as that of the fourth material layer (second topmost sublayer of strained superlattice layer 23’) (claim 2), further comprising a plurality of vertical heterojunctions (vertical junctions of x and y) between the first material (material corresponding to x) and the second material (material corresponding to y) alternately arranged in the periodically ordered relation in the horizontal direction (claim 7).
Claims 1 and 5-8 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Cheng (WO 2015/054982)
Regarding claims 1 and 5-8, Cheng discloses a semiconductor device (Fig. 2A), comprising: a substrate (bottommost white/blank portion of silicon substrate 1) (line 25 of page 6 and line 33 of page 7 of translation of WO 2015/054982); a nucleation layer (3; nitride buffer layer) (line 35 of page 7), because the limitation “nucleation” is directed to a product by process limitation and/or an intended use of a layer on which a layer is or layers are subsequently deposited, disposed on the substrate, because the preposition “on” does not necessarily suggest “directly on”; a buffer layer (10; semiconductor composite structure) (line 33 of page 7) disposed on the nucleation layer, because (a) the limitation “buffer” is also directed to a product by process limitation and/or an intended use of a layer on which a layer is or layers are subsequently deposited, and (b) the preposition “on” does not necessarily suggest “directly on”, the buffer layer comprising: a superlattice layer (superlattice of n-Si and p-Si), comprising a first material (n-Si) and a second material (p-Si) alternately arranged in a periodically ordered relation in a horizontal direction; a third material layer (topmost white/blank layer of 1) disposed on top surfaces of the first material and the second material of the superlattice layer, wherein the third material layer comprises a single material composition continuously extending directly over all of the top surfaces of the first material (n-Si) and the second material (p-Si) of the superlattice layer (10); a fourth material layer (2; Core layer), stacked in sequence with the third material layer in a vertical direction; an active layer (composite layer of 4 (nitride channel layer) and 5 (nitride barrier layer)) (lines 39-40 of page 7) disposed on the buffer layer (10); and a gate electrode (8) (line 49 of page 7) disposed on the active layer (claim 1), wherein the active layer (composite layer of 4 and 5) comprises a channel layer (4) and a barrier layer (5) stacked from bottom to top on the buffer layer (claim 5), further comprising a heterojunction between the third material layer (topmost white/blank layer of 1) and the fourth material layer (2), and the heterojunction continuously extending along the horizontal direction (claim 6), further comprising a plurality of vertical heterojunctions between the first material (n-Si) and the second material (p-Si) alternately arranged in the periodically ordered relation in the horizontal direction (claim 7), wherein the first material (n-Si) and the second material (p-Si) of the superlattice layer (10) directly contact the single material composition of the third material layer (topmost white/blank layer of 1) (claim 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (WO 2015/054982)
Regarding claim 1, Cheng discloses a semiconductor device (Fig. 2A), comprising: a substrate (bottommost white/blank portion of silicon substrate 1) (line 25 of page 6 and line 33 of page 7 of translation of WO 2015/054982); a nucleation layer (2; core layer) (line 35 of page 7), because the limitation “nucleation” is directed to a product by process limitation and/or an intended use of a layer on which a layer is or layers are subsequently deposited, disposed on the substrate, because the preposition “on” does not necessarily suggest “directly on”; a buffer layer (10; semiconductor composite structure) (line 33 of page 7) disposed on the nucleation layer, because (a) the limitation “buffer” is also directed to a product by process limitation and/or an intended use of a layer on which a layer is or layers are subsequently deposited, and (b) the preposition “on” does not necessarily suggest “directly on”, the buffer layer comprising: a superlattice layer (superlattice of n-Si and p-Si), comprising a first material (n-Si) and a second material (p-Si) alternately arranged in a periodically ordered relation in a horizontal direction; a third material layer ((portion of) 3 (having uniform material composition)) disposed on top surfaces of the first material and the second material of the superlattice layer, wherein the third material layer comprises a single material composition continuously extending directly over all of the top surfaces of the first material and the second material of the superlattice layer; an active layer (composite layer of 4 (nitride channel layer) and 5 (nitride barrier layer)) (lines 39-40 of page 7) disposed on the buffer layer (10); and a gate electrode (8) (line 49 of page 7) disposed on the active layer.
Cheng differs from the claimed invention by not comprising a fourth material layer, stacked in sequence with the third material layer in a vertical direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Cheng can further comprise a fourth material layer, stacked in sequence with the third material layer in a vertical direction, because even though Cheng shows one nitride buffer layer 3 in Fig. 2-A, a plurality of nitride buffer layers have been commonly formed in manufacturing GaN-based semiconductor devices to reduce lattice mismatch between the substrate and the device layers, to prevent warpage of the GaN-based semiconductor devices during cooling of the semiconductor layers, and to improve quality of the semiconductor layers formed on the buffer layer; in this case, one of the plurality of buffer layers can be referred to as the fourth material layer.
Regarding claims 3 and 4, Cheng differs from the claimed invention by not showing that the third material layer or the fourth material layer comprises aluminum gallium nitride (claim 3), and the third material layer and the fourth material layer respectively comprise Alₓ₁Ga₁-ₓ₁N with x1 being a constant greater than 0 and less than 1, and Alₓ₃Ga₁-ₓ₃N, with x3 being a constant greater than 0 and less than 1, and x3 is different from x1 (claim 4).
Cheng further discloses that “nitride buffer layer 3 includes GaN or A1N [sic] or other nitrides” on lines 36-37 of page 7.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the third material layer or the fourth material layer can comprise aluminum gallium nitride, and the third material layer and the fourth material layer can respectively comprise Alₓ₁Ga₁-ₓ₁N with x1 being a constant greater than 0 and less than 1, and Alₓ₃Ga₁-ₓ₃N, with x3 being a constant greater than 0 and less than 1, and x3 is different from x1, because (a) an AlGaN layer and a plurality of AlGaN layers has/have been commonly employed in manufacturing GaN-based semiconductor devices due to its or their well-known physical and electrical characteristics such as a band gap of the AlGaN layer and band gaps of the AlGaN layers, and its or their lattice matching characteristics between the substrate and the semiconductor layers deposited on the AlGaN layer(s), and (b) it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use, In re Leshin, 125 USPQ 416.
Regarding claims 5 and 7, Cheng further discloses for the semiconductor device according to claim 1 that the active layer (composite layer of 4 and 5) comprises a channel layer (4) and a barrier layer (5) stacked from bottom to top on the buffer layer (claim 5), further comprising a plurality of vertical heterojunctions between the first material (n-Si) and the second material (p-Si) alternately arranged in the periodically ordered relation in the horizontal direction (claim 7).
Response to Arguments
Applicants’ arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicants’ arguments in the REMARKS filed March 5, 2026 are not persuasive, because (a) Applicants’ arguments are primarily based on a narrow definition of the preposition “on”, which Merriam-Webster dictionary defines as being “used as a function word to indicate position in close proximity with”, (b) in other words, the preposition “on” does not necessarily suggest “directly on”, “above”, “over” or “in direct (physical) contact with”, (c) furthermore, Applicants’ arguments are based on a positional relationship of the claimed component layers that Applicants do not claim in claim 1, and (d) for example, even though a fly sits underneath a ceiling, one can say that the fly sits on the ceiling, and even though a third floor of a building is separated from a first floor, the third floor is on the first floor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gao et al. (US 10,128,228)
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 July 14, 2026
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