Prosecution Insights
Last updated: August 17, 2026
Application No. 18/632,669

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §102§103
Filed
Apr 11, 2024
Priority
Apr 25, 2023 — TW 112115328
Examiner
PARENDO, KEVIN A
Art Unit
Tech Center
Assignee
Winbond Electronics Corp.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
553 granted / 765 resolved
+12.3% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
36 currently pending
Career history
794
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
48.8%
+8.8% vs TC avg
§102
19.8%
-20.2% vs TC avg
§112
28.2%
-11.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 765 resolved cases

Office Action

§102 §103
DETAILED ACTION Election/Restrictions A restriction requirement was mailed on 5/6/26. Applicant's election with traverse of Group II (claims 12-19) in the reply filed on 5/6/26 is acknowledged. The traversal is on the ground(s) that there is “no undue burden” to examine both Groups I and II. This is not found persuasive because of the detailed reasons set forth in sections 2-3 of the 7/2/26 restriction requirement. The requirement is still deemed proper and is therefore made FINAL. Claims 1-11 are withdrawn. Foreign Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 4/11/24 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 12, 14, and 15 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2021/0118887 A1 (“Kuo”). Kuo teaches, for example: PNG media_image1.png 553 666 media_image1.png Greyscale Kuo teaches: 12. A semiconductor structure (see e.g. 1 in Fig. 2), comprising: a substrate 101 comprising a plurality of first active regions (e.g. 111a’/121C and 111c’/121m) and a second active region (e.g. 111b’), wherein each of the first active regions has an upper portion (e.g. 121C and 121m) and a lower portion (e.g. 111a’ and 111c’) supporting the upper portion, wherein a bottom width of the upper portion is greater than a top width of the lower portion (see e.g. Fig. 2), and wherein each of the first active regions has a hammer-shaped profile (each is generally wider on the top than on the bottom, having a roughly T-shape, which is interpreted as well as a “hammer-shape”); and a trench isolation structure 113” disposed between the adjacent first active regions, wherein the second active region is separated from the first active regions by the trench isolation structure (see e.g. Fig. 2), and wherein a top surface of the second active region is not greater than a top surface of the lower portion of the first active regions (see e.g. Fig. 2, wherein a top of 111b’ is the same width as the top of 111a’ and 111c’). 14. The semiconductor structure as claimed in claim 12, wherein a top width of the upper portion of each of the first active regions is greater than a top width of the second active region (see e.g. Fig. 2). 15. The semiconductor structure as claimed in claim 12 (in this claim, the first active regions may be interpreted as 112h/111b’, of which there are multiple as shown in Fig. 1; and the second active regions may be interpreted as 121C/111a’ and 121m/111c’ by switching said interpretation in claim 12 for this interpretation), further comprising: a bit line contact structure 151a (see e.g. para 43 and Fig. 2) disposed on the second active region; and a bit line structure (see e.g. para 6, 17, 43) disposed on the bit line contact structure. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo in view of US 8133786 B2 (“Lee”). Kuo teaches claim 12, as discussed above, but does not specifically teach: 13. The semiconductor structure as claimed in claim 12, wherein a width of the lower portion of each of the first active regions and a width of the second active region taper from bottom to top. Lee teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Kuo, wherein a width of the lower portion of each of the first active regions and a width of the second active region taper from bottom to top (see e.g. Fig. 16A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lee to the invention of Kuo. The motivation to do so is that the combination produces the predictable results of having a complex shape, including at least some portions that are tapered, due to the various etching steps used to form the isolation trenches (see e.g. col 13 lines 8-64). Claim(s) 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo in view of US 8143121 B2 (“Lin”). Kuo teaches claims 12 and 15, as discussed above, but not specifically: 17. The semiconductor structure as claimed in claim 15, further comprising: a storage node contact structure disposed on the upper portion of each of the first active regions; a landing pad disposed on the storage node contact structure; and a capacitive structure disposed over the storage node contact structure, wherein each of the first active regions, the storage node contact structure, the landing pad, and the capacitive structure are electrically connected; or 19. The semiconductor structure as claimed in claim 12, wherein a top width of the upper portion of each of the first active regions is equal to the bottom width of the upper portion of each of the first active regions. Lin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Kuo: 17. The semiconductor structure as claimed in claim 15, further comprising: a storage node contact structure (comprising one or more of “capacitor contact pillars 84a”, “epitaxial silicon 64”, and/or “heavily doped diffusion contact region 62”) disposed on the upper portion of each of the first active regions; a landing pad (e.g. “landing pad 94”) disposed on the storage node contact structure; and a capacitive structure (e.g. “storage capacitor 96”) disposed over the storage node contact structure, wherein each of the first active regions, the storage node contact structure, the landing pad, and the capacitive structure are electrically connected; and 19. The semiconductor structure as claimed in claim 12, wherein a top width of the upper portion of each of the first active regions is equal to the bottom width of the upper portion of each of the first active regions (see equal width of 10a at its top and near a lower part of 10a, before it flares out where it touches 10b; the “upper portion” and the “lower portion” are not claimed in a way that distinguishes where said portions must occur in any uniform or nonuniform shape). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lin to the invention of Kuo. The motivation to do so is that the combination produces the predictable results of connecting storage capacitors to the transistors in a series configuration that is a stacked capacitor, allowing for a minimized area (see e.g. “background of the invention” section). Allowable Subject Matter Claim(s) 16 and 18 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 16 or 18, including: 16. The semiconductor structure as claimed in claim 15, wherein a top surface of the bit line contact structure is level with a top surface of the upper portion of the first active regions (see wherein in Kuo, the top of the electrode 151a is much higher than the top of the active regions 121c or 121h; this is also true in Lin (see e.g. cover figure); and 18. The semiconductor structure as claimed in claim 17, wherein each of the first active regions and the second active region is an elongated structure in a top view, wherein the bit line contact structure corresponds to a central position of the second active region in the top view, and wherein the storage node contact structure corresponds to an end position of each of the first active regions in the top view (these are not specifically taught in the cited prior art). The other claims each depend from one of these claims, and each would be allowable for the same reasons as the claim from which it depends. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Conclusion / Prior Art The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited. US 8143121 B2 (“Lin”) (cover), US 8133786 B2 (Fig. 16A) (“Lee”), and US 2022/0181326 A1 (Fig. 8C), US 2019/0252550 A1 (“Huang”) (cover) teach active region having a top shape wider than a bottom shape. Conclusion / Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Kevin Parendo/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Apr 11, 2024
Application Filed
Jul 30, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
84%
With Interview (+11.2%)
2y 8m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 765 resolved cases by this examiner. Grant probability derived from career allowance rate.

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