DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I corresponding to claims 1-6 in the reply filed on 06/08/2026 is acknowledged.
Claims 7-12 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/08/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/11/2024 was filed after the mailing date of the application on 04/11/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Knoll et al, US 20190363166 A1 (Knoll).
Regarding claim 1; Knoll teaches a semiconductor device (Knoll: Fig (1): 100) comprising:
a semiconductor layer (2) having a first main surface (3) and a second main surface (4); and
a trench gate (10+11+19),
wherein the semiconductor layer (2) includes: a drift region (7) of a first conductivity type ([0116]: “7 (n.sup.−-doped) drift layer”);
a body region (6+15) of a second conductivity type ([0115]: “6, 26, 36, 46, 56, 86 (p-doped) base layer”) disposed closer to the first main surface (3) than the drift region (7),
the trench gate (10+11+19) is disposed in a trench that extends from the first main surface (3) of the semiconductor layer (2) to the drift region (7) through the body region (6+15),
a side surface of the trench gate (10+11+19) is in contact with the body region (6+15) and the drift region (7), and
of the body region (6+15) and the drift region (7), only the body region (6+15) has a channel region (15) in a portion that is in contact with the side surface of the trench gate (10+11+19), and
the channel region (15) has an impurity concentration that is lower than an impurity concentration of a portion of the body region (6+15) farther from the side surface of the trench gate (10+11+19) than the channel region (15, see paragraphs [0018] and [0019] for more details on this aspect: [0018]: “In an exemplary embodiment a mean value of the first local doping concentration in the channel region is less than 4.Math.10.sup.16 cm.sup.−3 or less than 2.Math.10.sup.16 cm.sup.−3. A low mean value of the first local doping concentration in the channel region as in these exemplary embodiments is an effective means to avoid any short channel effects, to reduce the subthreshold slope and to achieve a good off-state capability.” And [0019] In an exemplary embodiment a mean value of the second local doping concentration in the base layer is at least 5.Math.10.sup.17 cm.sup.−3 or at least 1.Math.10.sup.18 cm.sup.−3 or at least 5.Math.10.sup.18 cm.sup.−3. Such high doping concentration in the base layer can efficiently avoid reach-through breakdown in the blocking mode.”, see also [0053]).
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Regarding claim 2; Knoll teaches all the limitations of the semiconductor device according to claim 1.
Further, Knoll teaches wherein the impurity concentration of the second conductivity type of at least a part of the channel region (Knoll: Fig (1): 15) is half or less of the impurity concentration of the portion of the body region (6+15) farther from the side surface of the trench gate (10+11+19, see paragraphs [0018] and [0019] for more details on this aspect: [0018]: “In an exemplary embodiment a mean value of the first local doping concentration in the channel region is less than 4.Math.10.sup.16 cm.sup.−3 or less than 2.Math.10.sup.16 cm.sup.−3. A low mean value of the first local doping concentration in the channel region as in these exemplary embodiments is an effective means to avoid any short channel effects, to reduce the subthreshold slope and to achieve a good off-state capability.” And [0019] In an exemplary embodiment a mean value of the second local doping concentration in the base layer is at least 5.Math.10.sup.17 cm.sup.−3 or at least 1.Math.10.sup.18 cm.sup.−3 or at least 5.Math.10.sup.18 cm.sup.−3. Such high doping concentration in the base layer can efficiently avoid reach-through breakdown in the blocking mode.” , see also [0053]).
Regarding claim 4; Knoll teaches all the limitations of the semiconductor device according to claim 1.
Further, Knoll teaches wherein the side surface of the trench gate (Knoll: Annotated Fig (2) shared in this OA: 10+11+19) has a taper angle of 87 ° or more relative to a plane extending parallel to a bottom surface of the trench gate (by examining Fig (2) can be seen that the angle between the side surface of the trench gate relative to a plane extending parallel to a bottom surface of the trench gate is a right angle and thus appears to be more than 87 ⁰).
Regarding claim 5; Knoll teaches all the limitations of the semiconductor device according to claim 1.
Further, Knoll teaches wherein the channel region (Knoll: Annotated Fig (2) shared in this OA: 15) has a width of 40 nm or less ([0016]: “The thickness t.sub.CH of the channel region is in a range from 1 nm to 10 nm”) in a direction orthogonal to the side surface of the trench gate (10+11+19).
Regarding claim 6; Knoll teaches all the limitations of the semiconductor device according to claim 1.
Further, Knoll teaches wherein the semiconductor layer (Knoll: Fig (1): 2) is made of silicon carbide ([0020]: “In an exemplary embodiment the drift layer, the base layer, the channel region and the source layer are made of silicon carbide”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Knoll et al, US 20190363166 A1 (Knoll) in view of Tanaka et al, US 20220037474 A1 (Tanaka).
Regarding claim 3; Knoll teaches all the limitations of the semiconductor device according to claim 1.
Knoll does not teach wherein the semiconductor layer further includes an electric field relaxation region of the second conductivity type disposed to be in contact with a bottom surface of the trench gate.
Tanaka teaches wherein the semiconductor layer (Tanaka: Annotated Fig (1) shared in this OA: Semiconductor Layer) further includes an electric field relaxation region (51) of the second conductivity type disposed to be in contact with a bottom surface of the trench gate (7+8).
Knoll and Tanaka are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Knoll by constructing the electric field relaxation region as disclosed in Tanaka to reduce the leakage current from the device thus leading to a more efficient device.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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