DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I (claims 1-9 and 14-20) in the reply filed on July 01st, 2028 is acknowledged. The traversal is on the ground(s) that “Applicant believes that the Examiner’s search of Group I is likely to provide a proper search for Group II, and therefore respectfully submits that examinations of Group I and Group II will not present an undue burden and asks the Examiner to reconsider the restriction requirement”. This is not found persuasive because Group II can be formed by a materially different process and apparatus from Group I, and would require a unique text search in a different CPC clas.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statements (IDS) filed on April 11, 2024 and June 30, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner except as otherwise indicated.
Claim Objections
Claims 7 and 19 are objected to because of the following informalities: grammar. The phrase “10 Torr about 50 Torr” should read “10 Torr to about 50 Torr”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the term “about” on line 2 and line 3, respectively and claim 19 recites the term “about” on line 2 and line 3, respectively. Note that, the term “about” in claims 7 and 19 is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation renders the claim indefinite because this limitation does not quantify how much (i.e. a percentage or range) qualifies as "about". For examination purposes, the limitation will be interpreted as "less than 500 degrees" and "a range from 10 Torr.
Claim Rejections – 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
8. Claims 1-9 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Barbosa Lima et al (US 2021/0118679 A1, hereafter Barbosa) and Destefanis et al (US 2014/0024203 A1, hereafter Destefanis).
Regarding claim 1¸ Barbosa discloses a method of forming a doped semiconductor layer (Fig. 1 100; [0057]) in a semiconductor structure (Fig. 5 500; [0057]), comprising:
performing a first deposition process (Fig. 1 104; [0058]), a second deposition process (Fig. 1 106; [0058]) subsequent to the first deposition process (104), and an etch process (Fig. 1 108; [0058]),
the first deposition process (104) forming an n-type doped ([0011]) semiconductor layer (Fig. 5 302; [0063]) comprising a first n-type dopant ([0078]) on an exposed surface (Fig. 2 210+212; [0059]) of a substrate (Fig. 5 202+204; [0059])
the second deposition process (106) forming an n-type doped ([0011]) capping layer (Fig. 5 502; [0084]) on the doped semiconductor layer (302), the n-type doped capping layer (502) comprising a second n-type dopant ([0085]) different from the first n-type dopant ([0055], [0085]); and
the etch process (108) selectively removing ([0081]) a portion of the n-type doped semiconductor layer (Fig. 3 308; [0081]), and leaving an epitaxial portion (Fig. 3 302) of the n-type doped semiconductor layer (302), wherein
the n-type doped semiconductor layer (302) and the n-type doped capping layer (502) comprise silicon ([0065], [0084]).
Barbosa fails to disclose the etch process selectively removing an amorphous portion of the n-type doped semiconductor layer and an amorphous portion of the n-type doped capping layer.
Destefanis discloses an etch process (Figs. 3+4 portion 6 is etched away; [0042]) selectively removing an amorphous portion (Fig. 3 6; [0031]) of the doped semiconductor layer (Fig. 3 5+6; [0031]) and an amorphous portion (Fig. 3 6; [0031]) of the doped capping layer (Fig. 3 5+6; [0031], [0051] second layer formed not shown in figures). Destefanis is analogous to Barbosa in the field of epitaxial growth and etching processes for semiconductors.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the epitaxial growth and etch processes of Destefanis into the second deposition step of the process of Barbosa to form amorphous regions and etch them away for finer control over the dimensions of the semiconductor layer stack, providing desired device performance.
Regarding claim 2, Barbosa and Destefanis disclose the method of claim 1, wherein the first n-type dopant (Barbosa [0078]) comprises phosphorus (Barbosa [0055], it is known in the art that phosphine comprises of phosphorus).
Regarding claim 3, Barbosa and Destefanis disclose the method of claim 2, wherein the second n-type dopant (Barbosa [0085]) comprises arsenic, antimony, or both arsenic and antimony (Barbosa [0055]).
Regarding claim 4, Barbosa and Destefanis disclose the method of claim 1, wherein the first deposition process (104) comprises flowing a silicon-containing precursor (Barbosa [0068]) in a processing chamber (Barbosa Fig. 7 704; [0100]).
Regarding claim 5, Barbosa and Destefanis disclose the method of claim 4, wherein the second deposition process (106) comprises flowing the silicon-containing precursor ([0068]) and a second n-type dopant source (Barbosa [0085]-[0087]) in the processing chamber (704).
Regarding claim 6, Barbosa and Destefanis disclose the method of claim 5, wherein the etch process (108) comprises flowing an etchant gas (Barbosa [0081]) and a carrier gas (Destefanis [0041] vector gas is analogous to carrier gas) in a processing gas (Barbosa [0081], Destefanis [0041] etching atmosphere), subsequent to the second deposition process (106).
Regarding claim 7, Barbosa and Destefanis disclose the method of claim 6, wherein the first deposition process (104) and the second deposition process (106) are performed at a temperature less than 500 degrees Celsius (Barbosa [0061]) and at a pressure in a range from 10 Torr to 50 Torr (Barbosa [0062]).
Regarding claim 8, Barbosa and Destefanis disclose the method of claim 1, wherein the exposed surface (210+212) of the substrate (202+204) comprises one or more monocrystalline surfaces (Barbosa Fig. 2 210; [0059]) and one or more non-monocrystalline surfaces (Barbosa Fig. 2 212; [0059]), the epitaxial portion of the n-type doped semiconductor layer (Barbosa 308; [0048], [0063]) selectively formed on the one or more monocrystalline surfaces (Barbosa [0063]) and the amorphous portion of the n-type doped semiconductor layer (Destefanis 6; [0031]) formed on the one or more non-monocrystalline surfaces (Barbosa 212; Destefanis Fig. 3 surface of 3 analogous to Barbosa 212).
Regarding claim 9, Barbosa and Destefanis disclose the method of claim 1.
Barbosa and Destefanis fails to explicitly disclose a third deposition process performed subsequent to the second deposition process, the third deposition process forming an undoped semiconductor layer on the n-type doped capping layer.
However, Barbosa discloses disclose a third deposition process (Fig. 8 805; [0107]) performed subsequent to the second deposition process (804; [0107], analogous to 106) the third deposition process (805) forming an undoped semiconductor layer ([0107], Barbosa does not exclude undoped silicon to be used for this layer) on the n-type doped capping layer ([0107]).
Regarding claim 14¸ Barbosa discloses a processing system (Fig. 7 700; [0099]), comprising:
a processing chamber (Fig. 7 704; [0100]); and
a system controller (Fig. 7 728; [0100]) configured ([0118]) to cause the processing system (700) to:
performing a first deposition process (Fig. 1 104; [0058]), a second deposition process (Fig. 1 106; [0058]) subsequent to the first deposition process (104), and an etch process (Fig. 1 108; [0058]),
the first deposition process (104) forming an n-type doped ([0011]) semiconductor layer (Fig. 5 302; [0063]) comprising a first n-type dopant ([0078]) on an exposed surface (Fig. 2 210+212; [0059]) of a substrate (Fig. 5 202+204; [0059])
the second deposition process (106) forming an n-type doped ([0011]) capping layer (Fig. 5 502; [0084]) on the doped semiconductor layer (302), the n-type doped capping layer (502) comprising a second n-type dopant ([0085]) different from the first n-type dopant ([0055], [0085]); and
the etch process (108) selectively removing ([0081]) a portion of the n-type doped semiconductor layer (Fig. 3 308; [0081]), and leaving an epitaxial portion (Fig. 3 302) of the n-type doped semiconductor layer (302), wherein
the n-type doped semiconductor layer (302) and the n-type doped capping layer (502) comprise silicon ([0065], [0084]).
Barbosa fails to disclose the etch process selectively removing an amorphous portion of the n-type doped semiconductor layer and an amorphous portion of the n-type doped capping layer.
Destefanis discloses an etch process (Figs. 3+4 portion 6 is etched away; [0042]) selectively removing an amorphous portion ([0031]) of the doped semiconductor layer (Fig. 3 5+6; [0031]) and an amorphous portion ([0031]) of the doped capping layer (Fig. 3 5+6; [0031], [0051] second layer formed not shown in figures).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the epitaxial growth and etch processes of Destefanis into the second deposition step of the process of Barbosa to form amorphous regions and etch them away for finer control over the dimensions of the semiconductor layer stack, providing desired device performance.
Regarding claim 15¸ Barbosa and Destefanis discloses the processing system of claim 14, wherein the first n-type dopant (Barbosa [0078]) comprises phosphorus (Barbosa [0055], it is known in the art that phosphine comprises of phosphorus).
Regarding claim 16¸ Barbosa and Destefanis discloses the processing system of claim 15, wherein the first deposition process (104) comprises flowing a silicon-containing precursor (Barbosa [0068]) in a processing chamber (Barbosa Fig. 7 704; [0100]).
Regarding claim 17¸ Barbosa and Destefanis discloses the processing system of claim 16, wherein the second deposition process (106) comprises flowing the silicon-containing precursor ([0068]) and a second n-type dopant source (Barbosa [0085]-[0087]) in the processing chamber (704).
Regarding claim 18¸ Barbosa and Destefanis discloses the processing system of claim 17, wherein the etch process (108) comprises flowing an etchant gas (Barbosa [0081]) and a carrier gas (Destefanis [0041] vector gas is analogous to carrier gas) in a processing gas (Barbosa [0081], Destefanis [0041] etching atmosphere), subsequent to the second deposition process (106).
Regarding claim 19¸ Barbosa and Destefanis discloses the processing system of claim 18, wherein the first deposition process (104) and the second deposition process (106) are performed at a temperature less than 500 degrees Celsius (Barbosa [0061]) and at a pressure in a range from 10 Torr to 50 Torr (Barbosa [0062]).
Regarding claim 20¸ Barbosa and Destefanis discloses the processing system of claim 14, wherein the exposed surface (210+212) of the substrate (202+204) comprises one or more monocrystalline surfaces (Barbosa Fig. 2 210; [0059]) and one or more non-monocrystalline surfaces (Barbosa Fig. 2 212; [0059]), the epitaxial portion of the n-type doped semiconductor layer (Barbosa 308; [0048], [0063]) selectively formed on the one or more monocrystalline surfaces (Barbosa [0063]) and the amorphous portion of the n-type doped semiconductor layer (Destefanis 6; [0031]) formed on the one or more non-monocrystalline surfaces (Barbosa 212; Destefanis Fig. 3 surface of 3 analogous to Barbosa 212).
Conclusion
9. The following art made of record and not relied upon is pertinent to applicant’s disclosure.
Bauer et al (US 2012/0295427 A1) discloses forming an epitaxial layer and removing amorphous portions
Huang et al (US 2022/0375751 A1) discloses a cluster tool with a processing chamber and controller
Carlson et al (US 2006/0166414 A1) discloses growing monocrystalline and amorphous layers and etching away the amorphous portions
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL B SUN whose telephone number is (571)699-0231. The examiner can normally be reached Mon-Fri 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL B SUN/Examiner, Art Unit 2892
/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
Prosecution Insights