DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 09/15/2026 have been fully considered but they are not persuasive.
Regarding claim 8, Applicant argues FIG. 1 of Chung does not teach additional electrically isolating structures on two opposite sides of the first segment of the first gate DG. Further, Applicant argues, FIG. 3 of Chung shows the electrically isolating structure 120/152 is disposed under the first gate DG, and thus the electrically isolating structure 120/152 cannot have one or more segments on two opposite sides of the first gate DG along the second direction.
However, electrically isolating structure are not limited to those cited in the previous rejection. For example, FIG. 2A of Kim shows electrically isolating structures 124 overlapping active regions FA in the third direction. In another example, FIG. 3 of Chung shows electrically isolating structures 152 overlapping the first active region FA1 and the second active region FA2.
Therefore, the previous rejections over Kim and Chung stand. See below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 8 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 20210134796 A1; hereinafter Kim).
Regarding claim 8, FIGS. 1-2F of Kim teach a semiconductor device (e.g. FIG. 1), comprising: a first active region (first instance of FA ¶ [0017]) extending along a first direction (x direction); a second active region (second instance of FA ¶ [0017]) extending along the first direction (x direction); an isolation structure (112 ¶ [0019]) extending between the first active region (first instance of FA) and the second active region (second instance of FA, see FIG. 2D); and a first gate (first instance of GL ¶ [0021]) extending along a second direction (y direction) perpendicular to the first direction (x direction), wherein the first gate (first instance of GL) has a first segment (first portion of first instance of GL between first and second instances of FA) overlapping the isolation structure (112) in a third direction (z direction) substantially perpendicular to the first direction (x direction) and the second direction (y direction, see FIGS. 1 and 2D), and wherein the first segment (first portion of first instance of GL between first and second instances of FA) is free from overlapping the first active region (first instance of FA) and the second active region (second instance of FA) in the third direction (z direction, see Examiner annotated FIG. 1 below); a first electrically isolating structure (first instance of 124 overlapping first instance of FA, ¶ [0020], see FIG. 2A) overlapping the first active region (first instance of FA) along the third direction (z direction); and a second electrically isolating structure (second instance of 124 overlapping second instance of FA, see FIG. 2A) overlapping the second active region (second instance of FA) along the third direction (z direction), wherein the first electrically isolating structure (first instance of 124) and the second electrically isolating structure (second instance of 124) are disposed on two opposite sides, along the second direction (y direction), of the first segment of the first gate (first portion of first instance of GL between first and second instances of FA).
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Claim 8 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung (US 20160260715 A1; hereinafter Chung).
Regarding claim 8, FIGS. 1-3 of Chung teaches a semiconductor device (e.g. FIG. 1), comprising: a first active region (FA1 ¶ [0033]) extending along a first direction (x direction); a second active region (FA2 ¶ [0033]) extending along the first direction (x direction); an isolation structure (120 ¶ [0034]) extending between the first active region (FA1) and the second active region (FA2); and a first gate (DG ¶ [0034]) extending along a second direction (y direction) perpendicular to the first direction (x direction), wherein the first gate (DG) has a first segment (first portion of DG between FA1 and FA2) overlapping the isolation structure (120) in a third direction (z direction) substantially perpendicular to the first direction (x direction) and the second direction (y direction), and wherein the first segment (first portion of DG between FA1 and FA2) is free from overlapping the first active region (FA1) and the second active region (FA2) in the third direction (z direction, see Examiner annotated FIG. 1 below); a first electrically isolating structure (first instance of 152 overlapping FA1 ¶ [], see FIG. 3) overlapping the first active region (FA1) along the third direction (z direction); and a second electrically isolating structure (second instance of 152 overlapping FA2, see FIG. 3) overlapping the second active region (FA2) along the third direction (z direction), wherein the first electrically isolating structure (first instance of 152) and the second electrically isolating structure (second instance of 152) are disposed on two opposite sides, along the second direction (y direction), of the first segment of the first gate (first portion of DG between FA1 and FA2). Note NGA and DG, including 152 and 162 shown in FIG. 3, extend beyond what is shown in FIG. 1. However, the first and second portions of DG do not extend beyond what is indicated in Examiner annotated FIG. 1 below.
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Allowable Subject Matter
Claims 9 and 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 9 recites the semiconductor device of claim 8, wherein the first gate has a second segment spaced apart from the first segment by the first electrically isolating structure, and the first electrically isolating structure overlaps the isolation structure in the third direction.
Kim teaches the semiconductor device of claim 8.
However, the prior art fails to teach or reasonably suggest “wherein the first gate has a second segment spaced apart from the first segment by the first electrically isolating structure, and the first electrically isolating structure overlaps the isolation structure in the third direction” together with all the limitations of claims 8 and 9 as claimed. Claims 11-13 contain allowable subject matter insofar as they depend upon and require all the limitations of claims 8 and 9.
Claims 1-6 and 14-22 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 1 recites a semiconductor device, comprising: a first active region extending along a first direction; a second active region extending along the first direction; a first gate extending along a second direction perpendicular to the first direction, wherein the first gate has a first segment continuously extending between the first active region and the second active region; and a first electrical conductor extending along the second direction and overlapping the first active region and the second active region in a third direction substantially perpendicular to the first direction and the second direction, and wherein the first segment is free from overlapping the first active region and the second active region in the third direction, and the first gate is free from overlapping the first active region and the second active region along the third direction.
FIGS. 1-3B of Cho et al. (US 20220102336 A1; hereinafter Cho) teach a semiconductor device (e.g. FIG. 2), comprising: a first active region (F1 ¶ [0026],[0037],[0051]) extending along a first direction (x direction); a second active region (F2 ¶ [0026],[0051]) extending along the first direction (x direction); a first gate (G1 ¶ [0038]) extending along a second direction (y direction) perpendicular to the first direction (x direction), wherein the first gate (G1) has a first segment (portion of G1 between F1 and F2) continuously extending between the first active region (F1) and the second active region (F2, see Examiner annotated FIG. 2 below); and a first electrical conductor (CA12 ¶ [0039]) extending along the second direction (y direction) and overlapping the first active region (F1) and the second active region (F2) in a third direction (z direction, see Examiner annotated FIG. 2 below) substantially perpendicular to the first direction (x direction) and the second direction (y direction), and wherein the first segment (portion of G1 between F1 and F2) is free from overlapping the first active region (F1) and the second active region (F2) in the third direction (z direction, see Examiner annotated FIG. 2 below).
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However, the prior art fails to teach or reasonably suggest “the first gate is free from overlapping the first active region and the second active region along the third direction” together with all the limitations of claim 1 as claimed. Claims 2-6 are allowable insofar as they depend upon and require all the limitations of claim 1.
Claim 14 recites a semiconductor device, comprising: a first active region extending along a first direction; a first gate extending along a second direction substantially perpendicular to the first direction, wherein the first gate comprises a first segment and a second segment spaced apart from the first segment along the second direction; and an electrically isolating structure overlapping the first gate in the second direction and overlapping the first active region in the first direction, wherein the electrically isolating structure overlaps the first active region along the third direction substantially perpendicular to the first direction and the second direction, and wherein the first segment is electrically isolated from the second segment by the electrically isolating structure.
FIGS. FIGS. 1-3 of Chung teach a semiconductor device (e.g. FIG. 1), comprising: a first active region (FA1 ¶ [0033]) extending along a first direction (x direction); a first gate (DG ¶ [0034]) extending along a second direction (y direction) substantially perpendicular to the first direction (x direction), wherein the first gate (DG) comprises a first segment (first segment of DG) and a second segment (second segment of DG) spaced apart from the first segment (first segment of DG) along the second direction (y direction); and an electrically isolating structure (120 ¶ [0034]) overlapping the first gate (DG) in the second direction (y direction) and overlapping the first active region (FA1) in the first direction (x direction, see FIGS. 1 and 3).
However, the prior art fails to teach or reasonably suggest “wherein the first segment is electrically isolated from the second segment by the electrically isolating structure” together with all the limitations of claim 14 as claimed. Claims 15-22 are allowable insofar as they depend upon and require all the limitations of claim 14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights