CTNF 18/633,485 CTNF 97664 TDETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-3 and 5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cho et al. (US 20220102336 A1; hereinafter Cho) . Regarding claim 1, FIGS. 1-3B of Cho teach a semiconductor device (e.g. FIG. 2), comprising: a first active region (F1 ¶ [0026],[0037],[0051]) extending along a first direction (x direction); a second active region (F2 ¶ [0026],[0051]) extending along the first direction (x direction); a first gate (G1 ¶ [0038]) extending along a second direction (y direction) perpendicular to the first direction (x direction), wherein the first gate (G1) has a first segment (portion of G1 between F1 and F2) continuously extending between the first active region (F1) and the second active region (F2, see Examiner annotated FIG. 2 below); and a first electrical conductor (CA12 ¶ [0039]) extending along the second direction (y direction) and overlapping the first active region (F1) and the second active region (F2) in a third direction (z direction, see Examiner annotated FIG. 2 below) substantially perpendicular to the first direction (x direction) and the second direction (y direction), and wherein the first segment (portion of G1 between F1 and F2) is free from overlapping the first active region (F1) and the second active region (F2) in the third direction (z direction, see Examiner annotated FIG. 2 below). PNG media_image1.png 736 1309 media_image1.png Greyscale Regarding claim 2, Cho teaches the semiconductor device of claim 1, and FIGS. 1-3B of Cho further teach further comprising: a second gate (G2 ¶ [0038]) extending along the second direction (y direction), wherein the second gate (G2) has a second segment (portion of G2 between F1 and F2) continuous extending between the first active region (F1) and the second active region (F2), and the second segment (portion of G2 between F1 and F2) overlaps the first segment (portion of G1 between F1 and F2) in the first direction (x direction, see Examiner annotated FIG. 2 below). PNG media_image2.png 739 1316 media_image2.png Greyscale Regarding claim 3, Cho teaches the semiconductor device of claim 2, and FIGS. 1-3B of Cho further teach wherein the first electrical conductor (CA12) is disposed between the first segment (portion of G1 between F1 and F2) and the second segment (portion of G2 between F1 and F2, see Examiner annotated FIG. 2 above). Regarding claim 5, Cho teaches the semiconductor device of claim 1, and FIGS. 1-3B of Cho further teach wherein the first electrical conductor (CA12) extends continuously between the first active region (F1) and the second active region (F2, see FIG. 2) . 07-15-03-aia AIA Claim s 1-2 and 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nam et al. (US 20180174953 A1; hereinafter Nam) . Regarding claim 1, FIG. 1 of Nam teaches a semiconductor device (e.g. FIG. 1), comprising: a first active region (first instance of 6 ¶ [0023]) extending along a first direction (1 st direction); a second active region (second instance of 6) extending along the first direction (1 st direction); a first gate (first instance of 16 ¶ [0023]) extending along a second direction (2 nd direction) perpendicular to the first direction (1 st direction), wherein the first gate (first instance of 16) has a first segment (first portion of first instance of 16 between first and second instances of 6) continuously extending between the first active region (first instance of 6) and the second active region (second instance of 6, see Examiner annotated FIG. 1 below); and a first electrical conductor (26 ¶ [0023]) extending along the second direction (2 nd direction) and overlapping the first active region (first instance of 6) and the second active region (second instance of 6) in a third direction (3 rd direction) substantially perpendicular to the first direction (1 st direction) and the second direction (2 nd direction), and wherein the first segment (first portion of first instance of 16 between first and second instances of 6) is free from overlapping the first active region (first instance of 6) and the second active region (second instance of 6) in the third direction (3 rd direction, see Examiner annotated FIG. 1 below). Regarding claim 2, Nam teaches the semiconductor device of claim 1, and FIG. 1 of Nam further teaches further comprising: a second gate (second instance of 16 ¶ [0026]) extending along the second direction (2 nd direction), wherein the second gate (second instance of 16) has a second segment (second portion of second instance of 16 between first and second instances of 6) continuous extending between the first active region (first instance of 6) and the second active region (second instance of 6), and the second segment (second portion of second instance of 16 between first and second instances of 6) overlaps the first segment (first portion of first instance of 16 between first and second instances of 6) in the first direction (1 st direction, see Examiner annotated FIG. 1 below). Regarding claim 4, Nam teaches the semiconductor device of claim 2, and FIG. 1 of Nam further teaches further comprising: a first gate connector (first instance of 56 ¶ [0023]) electrically connected to the first gate (first instance of 16) and disposed between the first active region (first instance of 6) and the second active region (second instance of 6); and a second gate connector (second instance of 56 ¶ [0023]) electrically connected to the second gate (second instance of 16), wherein the first gate connector (first instance of 56) is aligned to the second gate connector (second instance of 56, see FIG. 1) . PNG media_image3.png 773 1398 media_image3.png Greyscale 07-15-03-aia AIA Claim s 1-2, 6, 8-9, and 11-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 20210134796 A1; hereinafter Kim) . Regarding claim 1, FIGS. 1-2F of Kim teach a semiconductor device (e.g. FIG. 1), comprising: a first active region (first instance of FA ¶ [0017]) extending along a first direction (x direction); a second active region (second instance of FA ¶ [0017]) extending along the first direction (x direction); a first gate (first instance of GL ¶ [0021]) extending along a second direction (y direction) perpendicular to the first direction (x direction), wherein the first gate (first instance of GL) has a first segment (first portion of first instance of GL) continuously extending between the first active region (first instance of FA) and the second active region (second instance of FA, see Examiner annotated FIG. 1 below); and a first electrical conductor (CA2 ¶ [0035]) extending along the second direction (y direction) and overlapping the first active region (first instance of FA) and the second active region (second instance of FA) in a third direction (z direction) substantially perpendicular to the first direction (x direction) and the second direction (y direction), and wherein the first segment (first portion of first instance of GL) is free from overlapping the first active region (first instance of FA) and the second active region (second instance of FA) in the third direction (z direction, see Examiner annotated FIG. 1 below). Regarding claim 2, Kim teaches the semiconductor device of claim 1, further comprising: a second gate (second instance of GL ¶ [0021]) extending along the second direction (y direction), wherein the second gate (second instance of GL) has a second segment (second portion of second instance of GL) continuous extending between the first active region (first instance of FA) and the second active region (second instance of FA), and the second segment (second portion of second instance of GL) overlaps the first segment (first portion of first instance of GL) in the first direction (x direction, see Examiner annotated FIG. 1 below). Regarding claim 6, Kim teaches the semiconductor device of claim 2, further comprising: a cutting structure (CR ¶ [0031]) extending along the first direction (x direction), wherein the cutting structure (CR) cuts the first gate (first instance of GL) and the second gate (second instance of GL). PNG media_image4.png 766 1406 media_image4.png Greyscale Regarding claim 8, FIGS. 1-2F of Kim teach a semiconductor device (e.g. FIG. 1), comprising: a first active region (first instance of FA ¶ [0017]) extending along a first direction (x direction); a second active region (second instance of FA ¶ [0017]) extending along the first direction (x direction); an isolation structure (112 ¶ [0019]) extending between the first active region (first instance of FA) and the second active region (second instance of FA, see FIG. 2D); and a first gate (first instance of GL ¶ [0021]) extending along a second direction (y direction) perpendicular to the first direction (x direction), wherein the first gate (first instance of GL) has a first segment (first portion of first instance of GL between first and second instances of FA) overlapping the isolation structure (112) in a third direction (z direction) substantially perpendicular to the first direction (x direction) and the second direction (y direction, see FIGS. 1 and 2D), and wherein the first segment (first portion of first instance of GL between first and second instances of FA) is free from overlapping the first active region (first instance of FA) and the second active region (second instance of FA) in the third direction (z direction, see Examiner annotated FIG. 1 below). Regarding claim 9, Kim teaches the semiconductor device of claim 8, wherein the first gate (first instance of GL) has a second segment (second portion of first instance of GL between first and second instances of FA) spaced apart from the first segment (first portion of first instance of GL between first and second instances of FA) by an electrically isolating structure (instance of CR ¶ [0031]), and the electrically isolating structure (instance of CR) overlaps the isolation structure (112) in the third direction (z direction, see Examiner annotated FIG. 1 below). Regarding claim 11, Kim teaches the semiconductor device of claim 9, wherein the isolation structure (112) comprises a shallow trench isolation structure (see FIG. 2D). Regarding claim 12, Kim teaches the semiconductor device of claim 9, wherein the first active region (first instance of FA) has a first length in the second direction (first length of first instance of FA in y direction), and the electrically isolating structure (instance of CR) has a second length greater than the first length in the second direction (second length of instance of CR in y direction, see Examiner annotated FIG. 1 below). Regarding claim 13, Kim teaches the semiconductor device of claim 9, further comprising: a second gate (second instance of GL ¶ [0021]) comprising a third segment (third portion of second instance of GL between first and second instances of FA) overlapping the first segment (first portion of first instance of GL between first and second instances of FA) and the second segment (second portion of first instance of GL between first and second instances of FA) in the first direction (x direction, see Examiner annotated FIG. 1 below) . PNG media_image5.png 721 1313 media_image5.png Greyscale 07-15-03-aia AIA Claim s 8-10 and 14-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung (US 20160260715 A1; hereinafter Chung) . Regarding claim 8, FIGS. 1-3 of Chung teaches a semiconductor device (e.g. FIG. 1), comprising: a first active region (FA1 ¶ [0033]) extending along a first direction (x direction); a second active region (FA2 ¶ [0033]) extending along the first direction (x direction); an isolation structure (120 ¶ [0034]) extending between the first active region (FA1) and the second active region (FA2); and a first gate (DG ¶ [0034]) extending along a second direction (y direction) perpendicular to the first direction (x direction), wherein the first gate (DG) has a first segment (first portion of DG between FA1 and FA2) overlapping the isolation structure (120) in a third direction (z direction) substantially perpendicular to the first direction (x direction) and the second direction (y direction), and wherein the first segment (first portion of DG between FA1 and FA2) is free from overlapping the first active region (FA1) and the second active region (FA2) in the third direction (z direction, see Examiner annotated FIG. 1 below). Regarding claim 9, Chung teaches the semiconductor device of claim 8, wherein the first gate (DG) has a second segment (second segment of DG between FA1 and FA2) spaced apart from the first segment (first portion of DG between FA1 and FA2) by an electrically isolating structure (152 ¶ [0058]), and the electrically isolating structure (152) overlaps the isolation structure (120) in the third direction (z direction, see Examiner annotated FIG. 1 below). PNG media_image6.png 568 972 media_image6.png Greyscale Regarding claim 10, Chung teaches the semiconductor device of claim 9, wherein the electrically isolating structure (152) overlaps the first active region (FA1) in the third direction (z direction, see FIG. 3). Regarding claim 14, FIGS. FIGS. 1-3 of Chung teach a semiconductor device (e.g. FIG. 1), comprising: a first active region (FA1 ¶ [0033]) extending along a first direction (x direction); a first gate (DG ¶ [0034]) extending along a second direction (y direction) perpendicular to the first direction (x direction); and an electrically isolating structure (120 ¶ [0034]) overlapping the first gate (DG) in the second direction (y direction) and overlapping the first active region (FA1) in the first direction (x direction, see FIGS. 1 and 3). Regarding claim 15, Chung teaches the semiconductor device of claim 14, further comprising: a second active region (FA2 ¶ [0033]) extending along the first direction (x direction), wherein the first gate (DG) comprises a segment (portion of DG between FA1 and FA2) continuously extending the first active region (FA1) and the second active region (FA2, see Examiner annotated FIG. 1 below). Regarding claim 16, Chung teaches the semiconductor device of claim 15, wherein a length of the segment (length of portion of DG between FA1 and FA2) is less than a distance between the first active region (FA1) and the second active region (FA2) in the second direction (y direction). Regarding claim 17, Chung teaches the semiconductor device of claim 15, wherein the segment (portion of DG between FA1 and FA2) is free from overlapping the first active region (FA1) in a third direction (z direction) substantially orthogonal to the first direction (x direction) and the second direction (y direction, see Examiner annotated FIG. 1 below). Regarding claim 18, Chung teaches the semiconductor device of claim 17, wherein the segment (portion of DG between FA1 and FA2) is free from overlapping the second active (FA2) region in the third direction (z direction, see Examiner annotated FIG. 1 below). PNG media_image7.png 556 952 media_image7.png Greyscale Regarding claim 19, Chung teaches the semiconductor device of claim 15, further comprising: an isolation structure (112 ¶ [0039]) between the first active region (FA1) and the second active region (FA2), and the segment (portion of DG between FA1 and FA2) is disposed on the isolation structure (112, see Examiner annotated FIG. 3 below). Regarding claim 20, Chung teaches the semiconductor device of claim 14, wherein the first active region (FA1) has a first length in the second direction (first length of FA1 in y direction), and the electrically isolating structure (112) has a second length greater than the first length in the second direction (second length of 112 in y direction, see FIG. 3) . PNG media_image8.png 653 1207 media_image8.png Greyscale Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Claim 7 recites the semiconductor device of claim 1, wherein the first gate is free from overlapping the first active region and the second active region along the third direction. Cho teaches the semiconductor device of claim 1. However, the prior art fails to teach or reasonably suggest “wherein the first gate is free from overlapping the first active region and the second active region along the third direction” together with all the limitations of claims 1 and 7 as claimed . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nora T. Nix/Assistant Examiner, Art Unit 2891 /MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891 Application/Control Number: 18/633,485 Page 2 Art Unit: 2891 Application/Control Number: 18/633,485 Page 3 Art Unit: 2891 Application/Control Number: 18/633,485 Page 4 Art Unit: 2891 Application/Control Number: 18/633,485 Page 5 Art Unit: 2891 Application/Control Number: 18/633,485 Page 6 Art Unit: 2891 Application/Control Number: 18/633,485 Page 7 Art Unit: 2891 Application/Control Number: 18/633,485 Page 8 Art Unit: 2891 Application/Control Number: 18/633,485 Page 9 Art Unit: 2891 Application/Control Number: 18/633,485 Page 10 Art Unit: 2891 Application/Control Number: 18/633,485 Page 11 Art Unit: 2891 Application/Control Number: 18/633,485 Page 12 Art Unit: 2891
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