CTNF 18/633,920 CTNF 78914 DETAILED ACTION 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Office Action is in response to the communications dated 07/29/2024. Claims 1-20 are pending in this application. Specification 06-31 AIA 2. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 112 3. The following is a quotation of 35 U.S.C. 112: (b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 4. Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. Claims 1, 10, and 18 recite the limitations “ a first chip ” (claims 1, 10, 18) and “ a first carrier ” (claim 18), which is/are not clearly defined as to how they relate to other elements of the claimed inventions. The claim languages of these claims do not show any structural or functional relation between the claimed “a first chip” and/or “a first carrier” with other structures in the claims. Claims 1, 10, and 18 are therefore uncertainty and do not distinctly point out the subject matter(s) which is/are claimed as the Applicant’s invention. These claims are therefore indefinite. Claims 2-9, 11-17, and 19-20 are indefinite as well as these claims depend from claims 1, 10, and 18, respectively. Although an essential purpose of the examination process is to determine whether or not the claims define an invention that is both novel and nonobvious over the prior art, another essential purpose of patent examination is to determine whether or not the claims are precise, clear, correct, and unambiguous. The uncertainties of claim scope should be removed, as much as possible, during the examination process. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA 6. Claim s 1-2, 5-8, 10-11, and 14-16 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kim et al. (US 2010/0258936) Regarding claim 1, Kim discloses a semiconductor package, comprising: a first chip 100 (bottom chip 100, see fig. 5); a second chip 100 (top chip 100) having a lateral surface, a lower surface and a recess (facing gap-fill member 360) recessed with respect to the lower surface; a molding compound 370 on the lateral surface of the second chip 100; and a dielectric layer 360 within the recess; wherein the dielectric layer 360 is formed of a material different from that of the molding compound 370. Regarding claim 2, Kim discloses the semiconductor package as claimed in claim 1, wherein the first chip 100 comprises a first substrate (forming chip 100) and a first bonding layer 170 (fig. 2; para. 0053: coating layer 170 containing a hydrophilic substance; hydrophilic substance is well known a bonding substance) on the first substrate 100, the second chip 100 comprises a second substrate 100 and a second bonding layer 170 on the second substrate, and the dielectric layer 360 (fig. 5) disposed between the first bonding layer 170 and the second bonding layer 170. Regarding claim 5, Kim discloses the semiconductor package as claimed in claim 2, wherein the dielectric layer 360 (lipophilic, para. 0053) has a Young's modulus greater than that of the first bonding layer 170 (hydrophilic, para. 0052) and the second bonding layer 170. Regarding claim 6, Kim discloses the semiconductor package as claimed in claim 2, wherein the second bonding layer 170 of the second chip 100 has the lower surface and the recess recessed with respect to the lower surface of the second bonding layer. See fig. 5. Regarding claim 7, Kim discloses the semiconductor package as claimed in claim 1, wherein the recess is exposed form the lateral surface. See fig. 5. Regarding claim 8, Kim discloses the semiconductor package as claimed in claim 1, wherein the dielectric layer 360 has a thickness and a length, and a ratio of the length to the thickness is greater than 5. See fig. 5. Regarding claim 10, Kim discloses a semiconductor package, comprising: a first chip 100 (bottom chip 100, see fig. 5); and a second chip 100 (top chip 100) having a lateral surface; a molding compound 370 on the lateral surface of the second chip 100; and a dielectric layer 360 disposed between the first chip 100 and the second chip 100 and being contact with the molding compound 370. Regarding claims 11, 14-16, Kim discloses the semiconductor package comprising all claimed limitations. See the rejections of claims 2, 5-8, respectively . 07-15 AIA 7. Claim s 1, 7-8, 10, and 16 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Ko et al. (US 11,469,099) Regarding claim 1, Ko discloses a semiconductor package, comprising: a first chip 210 (see fig. 18); a second chip 220 having a lateral surface (facing molding material 400), a lower surface (facing the first chip 210) and a recess 225 recessed with respect to the lower surface; a molding compound 400 on the lateral surface of the second chip 220; and a dielectric layer 320/325 within the recess 225; wherein the dielectric layer 320/325 (col. 5, lines 22-27) is formed of a material different from that of the molding compound 400 (col. 5, lines 41-51). Regarding claim 7, Ko discloses the semiconductor package as claimed in claim 1, wherein the recess 215/225 is exposed form the lateral surface. See fig. 18. Regarding claim 8, Ko discloses the semiconductor package as claimed in claim 1, wherein the dielectric layer 320/325 has a thickness and a length, and a ratio of the length to the thickness is greater than 5. See fig. 18. Regarding claim 10, Ko discloses a semiconductor package, comprising: a first chip 210 (see fig. 18); and a second chip 220 having a lateral surface (facing molding material 400); a molding compound 400 on the lateral surface of the second chip; and a dielectric layer 320/325 disposed between the first chip 210 and the second chip 220 and being contact with the molding compound 400. Regarding claim 16, Ko discloses the semiconductor package as claimed in claim 10, wherein the dielectric layer 320/325 has a thickness and a length, and a ratio of the length to the thickness is greater than 5. See fig. 18 . Claim Rejections - 35 U.S.C. § 103 07-20-aia AIA 8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 9. Claim s 3, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2010/0258936) Regarding claims 3, and 12, Kim discloses the semiconductor package as claimed in claim 2, wherein the second substrate 100 has a thickness T1 (fig. 6). Kim does not particularly teach that the thickness T1 is greater than 50 micrometers. However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimension/thickness of the claimed element, and a device having the claimed relative dimension would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP §2144.04). It would have been obvious that a mere change in size of a component is generally recognized as being within the level of ordinary skill in the art. It is to be expected that a change in size, thickness would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955). The instant specification contains no disclosure of either the critical nature of the claimed dimension/thickness or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).) The claimed limitation regarding to the thickness of the second substrate does not bear any critical point that would establish patentability, and is not sufficient to patentable distinguish over the prior art, therefore being considered as unpatentable limitation(s) because it would have involve only a mere change in dimension/thickness of a component. A change in dimension/shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP §2144.04) . 07-21-aia AIA 10. Claim s 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 11,469,099, hereinafter, Ko ‘099) in view of Ko et al. (US 12,451,456, hereinafter, Ko ‘456) . Regarding claim 18, Ko ‘099 discloses a manufacturing method for a semiconductor package, comprising: providing a first carrier 100 or 210(see fig. 18); providing a second chip 210 or 220, wherein the second chip has a lateral surface (facing molding material 400), a lower surface (facing carrier 100) and a recess 215 or 225 recessed with respect to the lower surface; forming the dielectric layer 310/315 or 320/325 within the recess; forming a molding compound 400 on the lateral surface of the second chip 210/220. Ko ‘099 does not specifically disclose: forming at least one singulation passage passing through the molding compound and the first carrier, wherein the first carrier is singulated to form a first chip. Ko ‘456 discloses: A manufacturing method for a semiconductor package, comprising: providing a first carrier 20 or 30 (see figs. 5-6), providing a second chip 30 or 40, forming a molding compound 89 on a lateral surface of the second chip 30/40; forming at least one singulation passage 22-62 passing through the molding compound 89 and the first carrier 20/30, wherein the first carrier 20/30 is singulated to form a first chip 21/31 (col. 13, lines 41-67). It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Ko ‘099 so that the chips (including the first chip) can be formed by a singulating process, as that taught by Ko ‘456, for the benefit of low manufacturing cost due to multiple chip package being formed simultaneously. Regarding claim 19, Ko ‘099/Ko ‘456 discloses the manufacturing method as claimed in claim 18, wherein before forming the molding compound 400 on the lateral surface of the second chip, forming the dielectric layer 310/315 or 320/325 within the recess 215/225. See fig. 18 of Ko ‘099. Regarding claim 20, Ko ‘099/Ko ‘456 discloses the manufacturing method as claimed in claim 18, wherein the dielectric layer is formed of a material different from that of the molding compound. See col. 5, lines 22-27, and col. 5, lines 41-51 of Ko ‘099. Conclusion 11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)). A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633. /DAO H NGUYEN/Primary Examiner, Art Unit 2818 May 27, 2026 Application/Control Number: 18/633,920 Page 2 Art Unit: 2818 Application/Control Number: 18/633,920 Page 3 Art Unit: 2818 Application/Control Number: 18/633,920 Page 4 Art Unit: 2818 Application/Control Number: 18/633,920 Page 5 Art Unit: 2818 Application/Control Number: 18/633,920 Page 6 Art Unit: 2818 Application/Control Number: 18/633,920 Page 7 Art Unit: 2818 Application/Control Number: 18/633,920 Page 8 Art Unit: 2818 Application/Control Number: 18/633,920 Page 9 Art Unit: 2818
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