DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant’s election without traverse of Group, I, Species VI, claims 11, 12, 14 & 21-37 in the reply filed on 7/7/2026 is acknowledged.
Claims 11, 12, 14 & 21-37 are pending. Claims 1-10, 13 & 15-20 are cancelled. Claims 21-37 are new.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claims 11, 12, 14, 21-34 and 36-37 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pan et al. (US 2022/0302003).
Re claim 11, Pan teaches, under BRI, Fig. 7, [0119-0121], a semiconductor device package, comprising:
-a first electronic component (passive device 600);
-a second electronic component (dies 700, 800) disposed above the first electronic component (600),
-an interconnection structure (redistribution structure 440) configured to electrically connect the first electronic component (600) to the second electronic component (700, 800);
-a package material (432, 960) configured to encapsulate the first electronic component (600), the second electronic component (700, 800) and the interconnection structure (440);
wherein the interconnection structure (440) is arranged outside the first electronic component (600) and the second electronic component (700, 800) and surrounded by the package material (412, 960).
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Re claim 12, Pan teaches, Fig. 7, wherein the interconnection structure comprises a first redistribution layer (440) between the first electronic component (600) and the second electronic component (700, 800) and a first conductive element (interposer 500) connected to the first redistribution layer (440), and wherein the first electronic component (600) and the second electronic component (700, 800) are electrically connected to each other through the first redistribution layer (440) and the first conductive element (500).
Re claim 14, Pan teaches, Figs. 2A & 7, [0039], wherein the first conductive element (500) comprises a silicon material (510) and a through conductive via (514) passing through the silicon material (510).
Re claim 21, Pan teaches, Figs. 2A & 7, [0039], wherein the first conductive element comprises a conductive spacer (500), the silicon material (510) and the through conductive via (514) being comprised in the conductive spacer (500), and wherein the conductive spacer (500) is arranged at a side of the first electronic component (600) and surrounded by the package material (432, 960).
Re claim 22, Pan teaches, Fig. 2A, wherein the conductive spacer (500) further comprises a spacer redistribution layer (532) disposed on a lower surface of the silicon material (510) and electrically connected to the through conductive via (514), and a plurality of micro-bumps (under 532) disposed on the spacer redistribution layer (532).
Re claim 23, Pan teaches, under BRI, Figs. 2A & 7, wherein an upper surface of the conductive spacer (500) abuts against the first redistribution layer (440), and the through conductive via (consider 578, 568, 564, 514) is exposed at the upper surface of the conductive spacer (500) and electrically connected to the first redistribution layer (440).
Re claim 24, Pan teaches, Fig. 7, [0062], wherein the interconnection structure further comprises a second redistribution layer (410) disposed below the first electronic component (600), and the first conductive element (500) electrically connects the first redistribution layer (440) to the second redistribution layer (410).
Re claim 25, Pan teaches, Figs. 9-10, [0098-0100, 0103], an external connector (290) configured to electrically connect the first and second electronic components (600, 700, 800) to an external device (consider 100, 200), wherein the external connector (290) comprises a plurality of external electrical connections disposed on a lower surface of the second redistribution layer (410).
Re claim 26, Pan teaches, Fig. 9, [0098], wherein the external electrical connections comprise test pads or bonding pads (268).
Re claim 27, Pan teaches, Fig. 7, wherein the package material comprises a first molding compound (432) encapsulating the first electronic component (600) and a second molding compound (960) encapsulating the second electronic component (700, 800).
Re claim 28, Pan teaches, under BRI, Fig. 7, [0035, 0053, 0069, 0119-0121], a semiconductor device package, comprising:
-a first electronic component (600);
-a second electronic component (700, 800) disposed above the first electronic component (600);
-a first redistribution layer (440) disposed between the first electronic component (600) and the second electronic component (700, 800);
-a second redistribution layer (410) disposed below the first electronic component (600);
-a conductive spacer (500) arranged at a side of the first electronic component (600) and electrically connecting the first redistribution layer (440) to the second redistribution layer (410), such that the first electronic component (600) and the second electronic component (700, 800) are electrically connected to each other through the first redistribution layer (440), the conductive spacer (500) and the second redistribution layer (410); and
-a package material (432, 960) encapsulating the first electronic component (600), the second electronic component (700, 800) and the conductive spacer (500), wherein the conductive spacer (500) is arranged outside both the first electronic component (600) and the second electronic component (700, 800) and surrounded by the package material (432, 960).
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Re claim 29, Pan teaches, Fig. 2A, [0039], wherein the conductive spacer (500) comprises a silicon material (510) and a plurality of through silicon vias (514) surrounded by the silicon material (510).
Re claim 30, Pan teaches, Figs. 2A & 7, wherein the conductive spacer (500) further comprises a spacer redistribution layer (532) disposed on a lower surface of the silicon material (510) and electrically connected to the through silicon vias (514), and a plurality of micro-bumps (under 532) disposed on the spacer redistribution layer (532) and electrically connected to the second redistribution layer (410).
Re claim 31, Pan teaches, under BRI, Figs. 2A & 7, wherein an upper surface of the conductive spacer (500) abuts against the first redistribution layer (440), and the through conductive via (consider 578, 568, 564, 514) is exposed at the upper surface of the conductive spacer (500) and electrically connected to the first redistribution layer (440).
Re claim 32, Pan teaches, Figs. 9-10, [0098-0100, 0103], an external connector (290) comprising a plurality of external electrical connection disposed on a lower surface of the second distribution layer (410) and configured to electrically connect the first and second electronic components (600, 700, 800) to an external device (consider 100, 200).
Re claim 33, Pan teaches, Fig. 9, [0098], wherein the external electrical connections comprise test pads or bonding pads (268).
Re claim 34, Pan teaches, Fig. 7, wherein the package material comprises a first molding compound (432) encapsulating the first electronic component (600) and a second molding compound (960) encapsulating the second electronic component (700, 800).
Re claim 36, Pan teaches, Fig. 7, wherein the second electronic component (700, 800) comprises a component redistribution layer (formed by 492, 490, 448) on an active surface thereof facing the first redistribution layer (440), and the second electronic component (700, 800) is electrically connected to the first redistribution layer (440) through the component redistribution layer of the second electronic component (700, 800) and a plurality of electrical connections (under 448).
Re claim 37, Pan teaches, Fig. 7, wherein each of the first electronic component (600 as integrated passive device) and the second electronic component (700, 800 as HBM dies) comprises a known-good die, and each of the first redistribution layer (440) and the second redistribution layer (410) comprises a known-good redistribution layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Pan in view of Cho et al. (US 2012/0119388).
The teachings of Pan have been discussed above.
Re claim 35, Pan does not teach wherein the first electronic component comprises a component redistribution layer on an active surface thereof facing the second redistribution layer, and the first electronic component is electrically connected to the second redistribution layer through the component redistribution layer of the first electronic component and a plurality of electrical connections surrounded by the package material.
Cho teaches, Figs. 12-13, [0063, 0066, 0076], the first electronic component (124) comprises a component redistribution layer (132 with 134) on an active surface thereof facing the second redistribution layer (164), and the first electronic component (124) is electrically connected to the second redistribution layer (164) through the component redistribution layer of the first electronic component (124) and a plurality of electrical connections (170) surrounded by the package material (162).
As taught by Cho, one of ordinary skill in the art would utilize & modify the above teaching to obtain component redistribution layer and connections as claimed, because it aids in improving electrical connections in the formed package.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Cho in combination Pan due to above reason.
Conclusion
5. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Seol et al. (US 2017/0373035, Figs. 9 & 19) teaches fan out package module including a plurality of components mounted on a semiconductor chip.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/5/26
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