Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/24/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/12/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220173191 A1).
Regarding claim 1-2, 4, and 8-12, , Kim teaches, in FIG. 3, a display device comprising: a “substrate” (base layer) SUB; a first transistor T3 above the base layer, and comprising a first gate 510 and a first semiconductor pattern comprising a first source (see S3 in FIG. 2), a first active region 410 corresponding to the first gate, and a first drain (see D3 in FIG. 2); a second transistor T1 above the base layer and comprising an upper gate 310 (see [0134]) and a second semiconductor pattern comprising a second source (see S1 in FIG. 2), a second active 220 region below the upper gate, and a second drain (see D1 in FIG. 2); insulating layers covering (via insulating layers VIA1 and VIA2) the first transistor and the second transistor; a gate-insulating layer GI2 covering the second active region, and in which a first opening (opening in which 630 is disposed) corresponding to the second source, and a second opening (opening in which 640 is disposed) corresponding to the second drain, are defined; a first protective pattern (“connection pattern” 630, which can protect materials around it) above the second source, and comprising a same material as the upper gate ([0096] states that the upper gate may comprise molybdenum, aluminum, copper, nickel, chromium, or titanium, [0105] states that the first protective pattern may comprise molybdenum, aluminum, copper, nickel, chromium, or titanium); and a second protective pattern (“connection pattern” 640, which can protect materials around it) in the second opening, above the second drain, and comprising a same material as the upper gate ([0096] states that the upper gate may comprise molybdenum, aluminum, copper, nickel, chromium, or titanium, [0105] states that the second protective pattern may comprise molybdenum, aluminum, copper, nickel, chromium, or titanium). The examiner notes that the fact that the protective layer comprises metallic materials further proves that they are protective against light and outside particles.
While Kim lists many identical materials that can be used for the upper gate and the first and second protective layers, Kim does not explicitly teach that the upper gate and the first and protective layers are made of the same material.
It would have been obvious to one having ordinary skill in the art at the effective filing date to form the first and second protective layers out of a same material as the upper gate, [0090] states “Since the first lower electrode 110 is disposed on the same layer as the first lower gate electrode 120, the first lower electrode 110 may be formed together with the first lower gate electrode 120. Accordingly, a number of processes for forming the first lower electrode 110 and the first lower gate electrode 120 may be minimized,” one having ordinary skill in the art is motivated to form the first and second protective layers out of the same material as the upper gate so that the same concurrent deposition can be utilized and the same benefits garnered. The examiner notes that the upper gate and a portion of the protection layers are disposed in the same layer.
Regarding claim 2, Kim further teaches, in FIG. 3, that the second transistor further comprises a lower gate 120 below the second active region, wherein the lower gate and the upper gate are electrically connected to each other (the examiner notes that the upper electrode is referred to as the ([0029] states that a gate signal may be provided to the first lower gate electrode (120, the lower electrode) and [0014] states that a gate signal may be provided to the second lower electrode (this is the upper gate 310), thus they are both connected to the same signal) , wherein at least any one of the lower gate or the upper gate is configured to receive a separate signal (the separate signal being the gate signal, which at least one is configured to receive).
Kim does not teach that the upper and lower gates are electrically connected through a first contact hole passing through the gate-insulating layer and through a portion of the insulating layers between the lower gate and the upper gate.
However, Kim does disclose that the upper and lower electrodes are electrically connected
Applicant has not disclosed that connecting the upper and lower gates are through a first contact hole passing through the gate-insulating layer and through a portion of the insulating layers between the lower gate and the upper gate provides an advantage, is used for a particular purpose, or solves a stated problem other than the well-known and unsurprising function of electrically connecting the electrodes.
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the upper and lower gate electrodes of Kim with an electrical interconnect contact hole through the gate insulating layer and insulating layers between the upper and lower gates. This is because one of ordinary skill in the art would have expected such an interconnect to be one of several straightforward design variations of achieving an electrical interconnection between the upper and lower gate electrodes. Regarding claim 4, Kim further teaches, in FIG. 3, that a portion of the first protective pattern overlaps the gate-insulating layer, wherein a remaining portion of the first protective pattern does not overlap the gate-insulating layer (GI2), wherein a portion of the second protective pattern overlaps the gate-insulating layer, and wherein a remaining portion of the second protective pattern does not overlap the gate-insulating layer.
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Regarding claim 8, Kim further discloses that the first protective pattern comprise a protective pattern body, and a protective pattern protrusion portion protruding from the protective pattern body, and wherein at least a portion of the protective pattern protrusion portion overlaps the gate-insulating layer (see above annotated FIG. 3 and below annotated FIG. 3). The examiner notes that while only one of the protective patterns are depicted, both possess this structure, see FIG. 3.
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Regarding claim 9, Kim further teaches the protective pattern protrusion portion is provided in plurality (see directly above annotated FIG. 3), and wherein the protective pattern protrusion portions are spaced apart from each other along an outer side surface of each of the first protective pattern and the second protective pattern. Regarding claim 10, Kim further teaches that an inner side surface of the gate insulating layer opening comprises a first surface and a second surface (see directly above annotated FIG. 3) and that the protective pattern protrusion portion is provided in plurality (see above annotated FIG. 3), wherein the protective pattern protrusion portions are arranged along the second surface (that is, along the direction that the second surface is disposed, the up and down direction as is depicted in the cross section of FIG. 3), and wherein the second surface among the inner side surfaces is closest to the second active region.
Kim does not teach that the second surface is longer than the first surface.
Applicant has not disclosed that the second surface being longer than the first surface provides an advantage, is used for a particular purpose, or solves a stated problem other than the well-known and unsurprising function of providing an opening for the protective pattern.
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify second surface such that it is longer than the first surface. This is because one of ordinary skill in the art would have expected such an interconnect to be one of several straightforward design variations of providing an opening in the gate insulating layer for a protective layer. Regarding claim 11, Kim further teaches, in FIG. 3, that a portion of the gate-insulating layer contacts a lower surface of the upper gate and contacts an upper surface of the second active region.
Regarding claim 12, in an interpretation that is separate from the above interpretations of Kim, Kim teaches a first connection electrode contacting at least one of the first source or the first drain through a second contact hole passing through the insulating layers and the gate-insulating layer; and a second connection electrode contacting at least one of the first protective pattern or the second protective pattern through a third contact hole passing through the insulating layers and the gate-insulating layer. The examiner notes that portions of 630 and 640 which overlap the gate insulating layer GI2 are the protective patterns and portions which do not overlap the protective pattern make up the first connection electrode and second connection electrodes contacting the source and drain, respectively (passing through the insulating layers and contacting the first and second protective patterns, respectively) through second and third contact holes. A small portion of the second and third contact portions are disposed in the upper portion of the gate insulating layer as it appears in FIG. 3.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220173191 A1) in view of Lius (US 10763451 B2).
Regarding claim 3, as explained above, Kim teaches the limitations of claim 2. Kim further teaches, in [0090]: “Since the first lower electrode 110 is disposed on the same layer as the first lower gate electrode 120, the first lower electrode 110 may be formed together with the first lower gate electrode 120. Accordingly, a number of processes for forming the first lower electrode 110 and the first lower gate electrode 120 may be minimized.”
Kim does not teach that the lower gate is at a same layer as the first gate, and comprises a same material as the first gate.
Lius teaches, in FIG. 4B, a first transistor (comprising G2, “semiconductor layer” 409, S/D3, and S/D4) with a first gate G2 and a second transistor (comprising “semiconductor layer” 410, S/D5, S/D6, an upper gate electrode G4 above S/D5 and S/D6 and a lower gate electrode G3 below S/D5 and S/D6) in which the first gate electrode and the lower gate electrode are disposed in the same layer.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the disposition of the first gate electrode and the lower electrode taught by Kim such that they are in the same layer, as taught by Lius, and to form them in the same manufacturing step, as is suggested by Kim. One having ordinary skill in the art is motivated to do so in order to, for example, garner the benefits (“a number of processes . . . may be minimized”) taught by Kim above.
Claim(s) 5-7 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220173191 A1) in view of Noh (US 20220190079 A1).
Regarding claim 5, Kim further teaches, in FIG. 3, an insulating protrusion portion (defined by the inner surface of a hole in the gate insulating layer GI2 which protrudes into the gate insulating layer and in which the first protective layer is disposed) which overlaps with a portion of the first protective pattern.
Kim does not teach an insulating protrusion portion which overlaps the portion of both the first protective pattern and the second protective pattern.
Noh teaches, in FIG. 6, a first transistor 120 and a second transistor that has a gate insulating layer 115, source region 131b, drain region 131c, and channel region 131a. “drain electrode” 133 and “source electrode” are protective patterns (as they are disposed such that they protect the source and drain regions they correspond to) disposed in openings. An insulating protrusion portion is defined by an inner side surface of the gate-insulating layer, and at least a portion of the insulating protrusion portion overlaps the portion of the first protective pattern and the portion of the second protective pattern (see annotated FIG. 6 below). The examiner notes that the inner side surface of the protective layer is depicted only in cross-section in FIG. 6, and that the side surfaces are connected.
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It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Kim such that an insulating protrusion portion is defined by an inner side surface of the gate-insulating layer, and wherein at least a portion of the insulating protrusion portion overlaps the portion of the first protective pattern and the portion of the second protective pattern, as taught by Noh. One having ordinary skill in the art is motivated to do so in order to, for example, provide extra protection to the active layer (including the source, drain, and channel) from ambient light from above. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 6, Noh further teaches, in FIG. 6, that the insulating protrusion portion is provided in the plurality (see above annotated FIG. 6) and that are spaced apart from each other at regular intervals (because there are two insulating protrusion portions, the interval at which they are spaced apart is the one, regular interval).
It would have been obvious to one having ordinary skill in the art at the effective filing date to further modify the device taught by Kim such that the insulating protrusion portion is provided in plurality, and wherein the insulating protrusion portions are spaced apart from each other at regular intervals along the inner side surface, as taught by Noh. One having ordinary skill in the art is motivated to do so in order to, for example, decrease manufacturing complexity by patterning at regular intervals, increasing yield. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 7, Noh further teaches that the inner side surface comprises a first and second surface, and a tapered shape to the gate insulating layer (the second surface – shown in annotated FIG. 6 above - is therefore longer than the first surface), wherein the insulating protrusion portion is provided in the plurality and are arranged along the second surface, and wherein the second surface is closer to the active region than the first surface (see FIG. 6).
It would have been obvious to one having ordinary skill in the art at the effective filing date to further modify the device taught by Kim such that the inner side surface comprises a first surface, and a second surface that is longer than the first surface, wherein the insulating protrusion portion is provided in plurality, wherein the insulating protrusion portions are arranged along the second surface, and wherein the second surface is closer to the second active region than the first surface, as taught by Noh. One having ordinary skill in the art is motivated to do so in order to, for example, further ensure that the second active region is protected from ambient light (by providing more insulating protrusion portions, and providing them closer to the second active region, increasing the angle at which ambient light must be oriented in order to bypass the protrusion portion).
Regarding claim 13, Kim teaches a first and second semiconductor pattern, but does not teach that the first semiconductor pattern comprises a polysilicon semiconductor and that the second semiconductor pattern comprises an oxide semiconductor.
Noh teaches, in [0020]: “The first semiconductor pattern may include a polysilicon semiconductor, wherein the second semiconductor pattern includes an oxide semiconductor.” [0006] also teaches “Thin film transistors may be classified according to a material constituting a semiconductor layer. Among them, a low temperature poly-silicon (LTPS) thin film transistor and an oxide semiconductor thin film transistor are the most widely used transistors . . . display devices in which an LTPS thin film transistor and an oxide semiconductor thin film transistor are formed on the same substrate is being actively developed.” The examiner notes that LTPS semiconductors are polysilicon semiconductors.
It would have been obvious to one having ordinary skill in the art to modify the device taught by Kim such that the first semiconductor pattern comprises a polysilicon semiconductor and such that the second semiconductor pattern comprises an oxide semiconductor, as taught by Noh. One having ordinary skill in the art is motivated to use both a polysilicon and oxide “Since the polysilicon material has low energy consumption and excellent reliability due to high mobility (100 cm.sup.2/Vs or more) thereof, the LIPS thin film transistor may be applied to a multiplexer MUX and/or a gate driver for driving elements that drive thin film transistors for display elements” (Noh [0033]) and “Since the oxide semiconductor material has a bandgap greater than that of a silicon material, electrons do not pass the bandgap in an off state and thus, off-current is low. Accordingly, the oxide semiconductor thin film transistor is suitable for a switching thin film transistor having a short on-time and a long off-time” (Noh [0034]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220173191 A1) in view of Jang (US 20230008830 A1).
Regarding claim 14, Kim further teaches, in FIG. 1, that the display device comprises a “display region” (pixel region PNL) in which pixels (see “organic light emitting structure” 800 of FIG. 3) which overlap the first transistor and the second transistor (see FIG. 3), and a boundary region (comprising “data driver” DDV and “gate driver” GDV of FIG. 1).
Kim does not explicitly teach that the base layer comprises the boundary region, and does not teach that the boundary region opening is defined by the insulating and gate-insulating layers.
Jang teaches, in FIG. 5A, a display device comprising a base layer 110 in which the base layer comprises a “pixel area” PA overlapping a first transistor O-TFT and a second transistor S-TFT and a “boundary area” (boundary region) BA adjacent to the pixel region, and wherein a boundary opening BA-OP corresponding to the boundary region is defined by the insulating layers (“fifth insulating layer” 50 and “sixth insulating layer” 60, disposed on the transistors above the source regions SE1 and SE2, drain regions DE1 and DE1, and active regions AC1 and AC2) and the “fourth insulating layer” (which insulates the gate electrode GT2 from the active region, making this a gate electrode) 40.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Kim such that the base layer comprises a pixel region overlapping the first transistor and the second transistor, and a boundary region adjacent to the pixel region, and wherein a boundary opening corresponding to the boundary region is defined by the insulating layers and the gate-insulating layer, as taught by Jang. One having ordinary skill in the art is motivated to do so in order to, for example, ensure the isolation of electrodes between pixels regions. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220173191 A1) in view of S. Kim (US 20220093705 A1).
Regarding claim 15, as explained above, Kim teaches the limitations of claim 1. Kim does not teach that the base layer comprises a bending region.
S. Kim teaches, in FIG. 11, a display device comprising “substrate” (base layer) 100 and an “inorganic insulating layer” 110 comprising a “second insulating layer” 113 (which separates gate electrode G1 from an active region A1 and is therefore a gate insulating layer) and “third insulating layer” 114. FIG. 24 shows a “display area” DA (non-bending region) and a “bending area” BA that is bendable and is adjacent to the non-bending region, and wherein “The bending groove GR′ may mean an opening formed in the inorganic insulating layer [100] in the bending area BA.”([0189]).
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the display device taught by Kim such that the base layer comprises a non-bending region, and a bending region that is bendable and that is adjacent to the non-bending region, and wherein a bending groove overlapping the bending region is defined by the insulating layers and the gate-insulating layer, as taught by S. Kim. One having ordinary skill in the art is motivated to do so in order to, for example, enable a foldable display, increasing the economic viability of the product. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kwak (US 20170047357 A1) – Bending groove in display panel (see abstract).
Jeong (US 20190074304 A1) – Multiple gate electrodes over active area.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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