Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restriction - Response to Amendment
1. Applicant’s election without traverse of Embodiment 5, claims 1-2, 6-8, 11-12 and 14-16. Applicant's amendment dated 07/29/2026 in which claims 3-5, 9-10, 13 and 17-20 were canceled has been entered of record. Because applicant's amendment has canceled claims drawn to a distinct invention, the restriction requirement (dated 05/29/2026) is now moot. New claims 21-30 were added.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1-2, 6-8, 11-12, 14-16 and 21-30 are rejected under 35 U.S.C. 102(a1) as being anticipated by Jiang et al. (US 2011/0304010; hereinafter Jiang).
Regarding claim 1, Jiang, in fig. 3, discloses a semiconductor package, comprising: a first die (top die) comprising a through via structure RT1 and an electrostatic discharge (ESD) protection structure M1, wherein the ESD protection structure comprises: a resistance (the conductive line connect to the gate RGATE) coupled to the through via structure (RT1 & RPD); and an ESD protection element (gate terminal) coupled in series to the resistance (the conductive line connect to the gate RGATE), wherein a terminal of the ESD protection element (source/drain N+) is coupled to a substrate of the first die (top die).
Regarding claim 2, Jiang discloses further comprising a second die (bottom die) vertically coupled to the first die (top die) by a plurality of micro-bumps (fig. 3).
Regarding claim 6, Jiang discloses wherein the first die (top die) comprises one or more first load circuits therein (Rsub1) (fig. 3).
Regarding claim 7, Jiang discloses wherein the first die (top die) further comprises a through via barrier IL surrounding the through via structure to separate the through via structure (RT1 & RPD) from the one or more first load circuits therein (Rsub1) (fig. 3).
Regarding claim 8, Jiang discloses wherein the second die (bottom die) comprises one or more second load circuits therein (Rsub2) (fig. 3).
Regarding claim 21, Jiang discloses wherein the through via barrier vertically extends into a dielectric portion IL of the first die (top die) and laterally surrounds the through via structure (RT1 & RPD) (fig. 3).
Regarding claim 22, Jiang discloses wherein the through via structure (RT1 & RPD) vertically extends in the dielectric portion IL of the first die (top die) (fig. 3).
Regarding claim 23, Jiang discloses wherein a depth of the through via barrier vertically extending in the dielectric portion of the first die is greater than or equal to a depth of the through via structure vertically extending in the dielectric portion of the first die (fig. 3).
Regarding claim 24, Jiang discloses wherein a first terminal of the EDS protection element (gate terminal) is coupled to the resistance (the conductive line connect to the gate RGATE), and a second terminal of the EDS protection element (source/drain N+) is grounded (substrate) (fig. 3).
Regarding claim 11, Jiang, in fig. 3, discloses a semiconductor package, comprising: a first die (top die) comprising a through via structure (RT1 & RPD) and an electrostatic discharge (ESD) protection structure M1, wherein the ESD protection structure M1 comprises: a resistance (the conductive line connect to the gate RGATE) coupled to the through via structure (RT1 & RPD); and an ESD protection element (gate electrode of M1) coupled in series to the resistance (the conductive line connect to the gate RGATE); and a second die (bottom die) coupled to the first die (top die).
Regarding claim 12, Jiang discloses further comprising a second die (bottom die) vertically coupled to the first die (top die) by a plurality of micro-bumps (fig. 3).
Regarding claim 14, Jiang discloses wherein the first die (top die) further comprises a barrier structure IL surrounding the through via structure (RT1 & RPD) (fig. 3).
Regarding claim 15, Jiang discloses wherein the ESD protection structure M1 is deposited in a space defined between the through via structure (RT1 & RPD) and the barrier structure IL (fig. 3).
Regarding claim 16, Jiang discloses wherein a terminal of the ESD protection element (source/drain N+) is grounded (substrate) (fig. 3).
Regarding claim 25, Jiang discloses wherein the barrier structure vertically extends into a dielectric portion IL of the first die (top die) and laterally surrounds the through via structure (RT1 & RPD) (fig. 3).
Regarding claim 26, Jiang discloses wherein the through via structure (RT1 & RPD) vertically extends in the dielectric portion IL of the first die (top die) (fig. 3).
Regarding claim 27, Jiang discloses wherein a depth of the barrier structure vertically extending in a dielectric portion of the first die is greater than or equal to a depth of the through via structure extending in the dielectric portion of the first die (fig. 3).
Regarding claim 28, Jiang, in fig. 3, discloses a semiconductor package, comprising: a first die (top die) comprising a through via structure (RT1 & RPD), a through via barrier TI, and an electrostatic discharge (ESD) protection structure M1, wherein the through via barrier TI vertically extends into a dielectric portion TI of the first die (top die) and laterally surrounds the through via structure (RT1 & RPD), and wherein the ESD protection structure M1 comprises: a resistance (the conductive line connect to the gate RGATE) coupled to the through via structure (RT1 & RPD); and an ESD protection element, wherein a first terminal of the ESD protection element (gate terminal) is coupled to the resistance (the conductive line connect to the gate RGATE), and a second terminal of the ESD protection element (source/drain N+) is grounded (substrate); and a second die (bottom die).
Regarding claim 29, Jiang discloses wherein a depth of the through via barrier vertically extending in a dielectric portion of the first die is greater than or equal to a depth of the through via structure vertically extending in the dielectric portion of the first die (fig. 3).
Regarding claim 30, Jiang discloses wherein the second terminal of the ESD protection element (source/drain N+) is coupled to a substrate of the first die (top die) (fig. 3).
Conclusion
3. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818
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