DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 08/04/2026 has been accepted and entered. Claims 1-2 and 4-20 remain pending in this application. Applicant’s amendments to the Claims have overcome each and every 112(b) rejection previously set forth in the Non-Final Office Action mailed on 06/01/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US20220115280A1-Du80) in view of Jeoung et al. (US 20050243043 A1-Jeoung43).
Regarding claim 1, Du80 discloses a display device (Title) comprising:
a substrate (base substrate 1-Abstract L1-3, Fig 11) comprising
a display area (display 10, Fig. 1) and
a non-display area (base substrate comprising display area 10 and non-display area 20-Abstract L1-3, Fig 1);
pixels in the display area above the substrate (pixels PIX with pixel circuit 560 in display area 10 above base substrate 1-Fig 1, Fig 11);
an electrostatic discharge circuit in the non-display area above the substrate (electrostatic discharge circuit 43 comprising transistors T3, T4, T5, T6 in non-display area 20, wherein T3 (SD31/32, G31/32) being above substrate 1-Fig 1, Fig 10, Fig 11, [0066]);
a first line in the non-display area above the substrate (First line 51 in non-display area 20 on the same level as electrostatic discharge circuit 43 so on top of substrate 1-Fig 2, Fig 7, Fig 10), and
configured to receive a first voltage (First line 51 being the high-level signal line with a voltage between 6 and 8 V-[0063]L2-4);
a second line in the non-display area above the substrate (Second line 52 being in non-display area 20 on the same level as electrostatic discharge circuit 43 so on top of substrate 1-Fig 2, Fig 7, Fig 10), and
configured to receive a second voltage that is lower than the first voltage (Second line 52 being the low-level signal line with a voltage between -8 and -6 V-[0063]L2-9);
a first connection line connected between the first line and the electrostatic discharge circuit under the first line on the substrate (first/top connection line 61 of T3 connected between the first line 51 and the electrostatic discharge circuit 43 under the first line 51, all the lines being on the same level than G31 so on the substrate 1-Fig 7, [0066] L 49-55, Fig 10); and
a second connection line connected between the second line and the electrostatic discharge circuit under the second line on the substrate (Second/bottom connection line 61 of T6 connected between the second line 52 and the electrostatic discharge circuit 43 under the second line 52, all the lines being on the same level than G31 so on the substrate 1-Fig 7, [0066] L 49-55, Fig 10); and
data lines extending from the non-display area to the display area and connected to the pixels (Data lines DATAL extending from non-display area 20 to display area 10-Fig 1, [0047] L30-43).
Du80 does not disclose a display device comprising
an electrostatic discharge circuit comprising diode units comprising a first diode and a second diode;
one of the data lines comprising a first end connected to a node between the first diode and the second diode.
Jeoung43 teaches a display device comprising
an electrostatic discharge circuit comprising diode units comprising a first diode and a second diode (electrostatic discharge circuit 12 comprising diode units D1 and D2 comprising a first diode D1 and a second diode D2-Fig 1);
one of the data lines comprising a first end connected to a node between the first diode and the second diode (one of the data lines DL comprising a first end connected to a node between the first diode D1 and the second diode D2-Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Du80, as taught by Jeoung43 for the purpose of preventing static electricity (Jeoung43 : [0007]).
Regarding claim 2, Du80 and Jeoung43 combination discloses all the elements of claim 1, as noted above.
Du80 further discloses a display device
wherein the first line and the second line are spaced from each other with the electrostatic discharge circuit therebetween (first line 51 and second line 52 spaced apart by the electrostatic discharge circuit 43 therebetween-Fig 2), and
wherein the electrostatic discharge circuit is spaced from the first line and the second line by a same distance (first line 51 and second line 52 spaced apart by the electrostatic discharge circuit 43 comprising an even number of same type of transistors so spacing by a same distance-Fig 2).
Regarding claim 16, Du80 and Jeoung43 combination discloses all the elements of claim 1, as noted above.
Du80 further discloses a display device further comprising
a gate-driving circuit in the non-display area on the substrate (a gate-driving circuit 42 of 40 with Gate G1/G2 in the non-display area BB on the substrate 1-Fig 1, Fig 5, Fig 6), and
connected to the first line, the second line, and the pixels ( gate-driving gate 42 of 40 connected to pixels PIX through pad 32, to first line 51 through electrostatic discharge circuit 43, and second line 52 through electrostatic discharge circuit 43-Fig 1, Fig 3, Fig 4, Fig 5, [0065], [0052], [0054]).
Regarding claim 17, Du80 and Jeoung43 combination discloses all the elements of claim 16, as noted above.
Du80 further discloses a display device further comprising
wherein the first line and the second line comprise:
a first line portion connected to the electrostatic discharge circuit (first/top connection line 61 on T3 connected between first line 51 and electrostatic discharge circuit 43 beneath the first line 51-Fig 7, [0066] L 49-55, Fig 10); and
a second line portion connected to the gate-driving circuit (Second/bottom connection line 61/33 of T6 between the second line 52 and the electrostatic discharge circuit 43 under the second line 52, all the lines being on the same level than G31 so on the substrate 1-Fig 7, [0066] L 49-55, Fig 8, Fig 10), and
spaced apart from the first line portion (Connected to different TFT so spaced apart-Fig 7),
wherein the display device further comprises:
a first bridge line connecting the first line portion and the second line portion of the first line beneath the first line on the substrate (First bridge MUX1 of 33 connected to 426 of gate-driving circuit 42, connected to First line 51 through G3/4 so between first line portion and second line portion and beneath First line 51-Fig4, Fig 8, [0053]); and
a second bridge line connecting the first line portion and the second line portion of the second line beneath the second line on the substrate (Second bridge MUX2 of 33 connected to 427 of gate-driving circuit 42, connected to Second line 52 through G6/5-Fig 4, Fig 8, [0053]).
Regarding claim 18, Du80 and Jeoung43 combination discloses all the elements of claim 16, as noted above.
Du80 further discloses a display device further comprising
wherein the first line is configured to transmit a gate high voltage to the gate-driving circuit
(First line 51 configured to transmit a high-level signal VGH and connected to Gate-driving circuit 42-Fig 8, [0063] L1-4), and
wherein the second line is configured to transmit a gate low voltage to the gate-driving circuit (Second line 52 being the low-level signal line with a voltage between -8 and -6 V and connected to gate circuit 42-Fig 8, [0063] L1-9).
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US20220115280A1-Du80) in view of Jeoung et al. (US 20050243043 A1-Jeoung43), and further in view of Koo et al. (US20130050173A1-Koo73).
Regarding claim 4, Du80 and Jeoung43 combination discloses all the elements of claim 1, as noted above.
Du80 and Jeoung43 combination does not disclose a display device
wherein the first diode is connected between the first connection line and the one of the data lines, and
spaced from the first line by a first distance; and
wherein the second diode is connected between the second connection line and the one of the data lines, and
spaced from the second line by a second distance.
Koo73 teaches a display device
wherein the first diode is connected between the first connection line and the one of the data lines (First Diode from the Left connected first connection line Voff and one data line first left line of DLs-Fig 2A, Fig 2C), and
spaced from the first line by a first distance (Spaced by first distance corresponding to 122a height-Fig 2A, Fig 2C); and
wherein the second diode is connected between the second connection line and the one of the data lines (Second Diode from the Left connected second connection line Vcst and one data line second left line of DLs-Fig 2A, Fig 2D, [0042], [0043]), and
spaced from the second line by a second distance (Spaced by second distance corresponding to 124a height-Fig 2A, Fig 2C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Du80, as taught by Koo73 for the purpose of cutting off static electricity (Koo73: [0056]).
Regarding claim 5, Du80, Jeoung43, and Koo73 combination discloses all the elements of claim 4, as noted above.
Koo73 further teaches a display device
wherein the first distance and the second distance are substantially equal to each other (first distance corresponding to 122a height and second distance corresponding to 124a height being substantially equal-Fig 2A, Fig 2C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Du80, as taught by Koo73 for the purpose of cutting off static electricity (Koo73: [0056]).
Regarding claim 6, Du80, Jeoung43, and Koo73 combination discloses all the elements of claim 4, as noted above.
Koo73 further teaches a display device
wherein the first diode comprises
a first transistor diode-connected between the first connection line and the one of the data lines (electrostatic discharge circuit ESD1 having transistors 122a/124a being diode-coupled 121a/123a and First Diode from the Left connected first connection line Voff and one data line first left line of DLs so first transistor diode-connected between the first connection line Voff and the one of the data lines-[0034], Fig 2A, Fig 2C), and
wherein the second diode comprises
a second transistor diode-connected between the one of the data lines and the second connection line (electrostatic discharge circuit ESD1 having transistors 122a/124a being diode-coupled 121a/123a and Second Diode from the Left connected second connection line Vcst and one data line second left line of DLs so second transistor diode-connected between the second connection line Vcst and the one of the data lines-[0034], Fig 2A, Fig 2C, Fig 2D, [0042], [0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Du80, as taught by Koo73 for the purpose of cutting off static electricity (Koo73: [0056]).
Claim(s) 7-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US20220115280A1-Du80) in view of Jeoung et al. (US 20050243043 A1-Jeoung43), in view of Koo et al. (US20130050173A1-Koo73), and further in view of Liu et al. (US20210335984A1-Liu84).
Regarding claim 7, Du80, Jeoung43, and Koo73 combination discloses all the elements of claim 6, as noted above.
Koo73 further teaches a display device
wherein the diode units comprise a first transistor and a second transistor (diode units ESD1 comprising first transistor TFT1 and second transistor TFT2-Fig 3).
Du80, Jeoung43, and Koo73 combination does not teach a display device wherein
the first transistor and the second transistor comprising:
an active layer above the substrate;
a gate electrode above an insulating layer covering the active layer; and
a source electrode and a drain electrode above another insulating layer covering the gate electrode and
spaced apart from each other.
Liu84 teaches a display device wherein
the first transistor and the second transistor comprising:
an active layer above the substrate (active layer 30 above substrate 10-Fig 4);
a gate electrode above an insulating layer covering the active layer (gate electrode 50 above insulating layer 40-Fig 4); and
a source electrode and a drain electrode above another insulating layer covering the gate electrode (source electrode Left 70 and drain electrode Right 70 above insulating layer 60-Fig 4) and
spaced apart from each other (source electrode Left 70 and drain electrode Right 70 separated by gate electrode 50 so spaced apart from each other-Fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Du80 in view of Jeoung43, and further in view of Koo73, as taught by Liu84 for the purpose of solving the serious problem of voltage drop of the power lines by using anti-static area (Liu84:[0142]).
Regarding claim 8, Du80, Jeoung43, Koo73, and Liu84 combination discloses all the elements of claim 7, as noted above.
Liu84 further teaches a display device further comprising
conductive patterns overlapping a separation space between the source electrode and the drain electrode (source electrode Left 70 and drain electrode Right 70 separated by conductive patterns 90/51/71/72/73 so conductive patterns overlapping a separation space between the source electrode and the drain electrode-Fig 4),
beneath the source electrode and the drain electrode (conductive pattern 51 of conductive patterns 90/51/71/72/73 under source electrode Left 70 and drain electrode Right 70-Fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Du80 in view of Jeoung43, and further in view of Koo73, as taught by Liu84 for the purpose of solving the serious problem of voltage drop of the power lines by using anti-static area (Liu84:[0142]).
Regarding claim 9, Du80, Jeoung43, Koo73, and Liu84 combination discloses all the elements of claim 8, as noted above.
Liu84 further teaches a display device
wherein the conductive patterns cover the active layer in a separation space between the source electrode and the drain electrode (conductive pattern 90 of conductive patterns 90/51/71/72/73 covering active layer 30 in separation space between electrode Left 70 and drain electrode Right 70-Fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Du80 in view of Jeoung43, and further in view of Koo73, as taught by Liu84 for the purpose of solving the serious problem of voltage drop of the power lines by using anti-static area (Liu84:[0142]).
Regarding claim 10, Du80, Jeoung43, Koo73, and Liu84 combination discloses all the elements of claim 8, as noted above.
Liu84 further teaches a display device
wherein the conductive patterns overlap the gate electrode, the source electrode, and the drain electrode (conductive pattern 90 of conductive patterns 90/51/71/72/73 overlapping source electrode Left 70, drain electrode Right 70, and gate electrode 50-Fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Du80 in view of Jeoung43, and further in view of Koo73, as taught by Liu84 for the purpose of solving the serious problem of voltage drop of the power lines by using anti-static area (Liu84:[0142]).
Regarding claim 11, Du80, Jeoung43, Koo73, and Liu84 combination discloses all the elements of claim 8, as noted above.
Liu84 further teaches a display device
wherein the gate electrode is provided in a first gate conductive layer above the active layer (gate electrode 50 provided a first conductive layer 50 above active layer 30-Fig 4), and
wherein the conductive patterns are provided in a second gate conductive layer above an insulating layer covering the first gate conductive layer (conductive pattern 90 of conductive patterns 90/51/71/72/73 in a second gate conductive layer 90 above insulating layer 80 covering first gate conductive layer 50-Fig 4), or
provided in a third gate conductive layer above an insulating layer covering the second gate conductive layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Du80 in view of Jeoung43, and further in view of Koo73, as taught by Liu84 for the purpose of solving the serious problem of voltage drop of the power lines by using anti-static area (Liu84:[0142]).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US20250293511A1-Liu11) in view of Du et al. (US20220115280A1-Du80), and further in view of Jeoung et al. (US 20050243043 A1-Jeoung43).
Regarding claim 19, Liu11 discloses a display device (Title) comprising:
pixels in a display area (Pixels PX in display area AA-Fig 5);
data lines connected to the pixels (Data lines DL/111-Fig 5);
an electrostatic discharge circuit at a side of the display area (electrostatic discharge circuit 21/23 in side B1/B2-Fig 5), and
connected to the data lines (electrostatic discharge circuit 21/23 connected to Data lines 111-Fig 5);
a gate-driving circuit at another side of the display area (Gate-driving circuit 30 at another side B3/B4-Fig 5), and
connected to the pixels (Gate-driving circuit 30 connected to pixels PX with Gate lines GL-Fig 5);
a first line for transmitting a first voltage to the gate-driving circuit (First line PL1 transmitting High voltage VGH connected to lines 113, connected to gate-driving circuit-Fig 5, Fig 3, Fig 15, [0095]), and comprising
a first line portion connected to the electrostatic discharge circuit (PL1 portion connected to TS1 of electrostatic discharge circuit 21/23-Fig 3), and
a second line portion spaced apart from the first line portion (113 portion apart from PL1 portion, connected to gate-driving circuit, spaced apart from PL1 portion-Fig 5, Fig15) and
connected to the gate-driving circuit (113 portion apart from PL1 portion, connected to gate-driving circuit, spaced apart from PL1 portion-Fig 5, Fig15);
a second line for transmitting a second voltage to the gate-driving circuit (second line PL2 transmitting Low voltage VGHL1 connected to lines 113, connected to gate-driving circuit-Fig 5, Fig 3, Fig 15, [0095]), and comprising
a first line portion connected to the electrostatic discharge circuit ( Pl2 portion connected to TS4 of electrostatic discharge circuit 21/23-Fig 3), and
a second line portion spaced from the first line portion (113 portion apart from PL2 portion, connected to gate-driving circuit, spaced apart from PL2 portion-Fig 5, Fig15) and
connected to the gate-driving circuit (PL2 portion apart from 113 portion, connected to gate-driving circuit through 113, spaced apart from 113 portion by 23-Fig 5, Fig15);
Liu11 does not disclose a display device comprising
an electrostatic discharge circuit comprising diode units comprising a first diode and a second diode,
one of the data lines comprising a first end connected to a node between the first diode and the second diode;
a first bridge line connected between the first line portion and the second line portion of the first line beneath the first line; and
a second bridge line connected between the first line portion and the second line portion of the second line beneath the second line.
Du80 teaches a display device
a first bridge line connected between the first line portion and the second line portion of the first line beneath the first line (First bridge MUX1 of 33 connected to 426 of gate-driving circuit 42, connected to First line 51 through G3/4 so between first line portion and second line portion and beneath First line 51-Fig4, Fig 8, [0053]); and
a second bridge line connected between the first line portion and the second line portion of the second line beneath the second line (Second bridge MUX2 of 33 connected to 427 of gate-driving circuit 42, connected to Second line 52 through G6/5-Fig 4, Fig 8, [0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Du80, as taught by Liu84 for the purpose of improving a product yield of the OLED display apparatus (Du80: [0004]).
Du80 does not disclose a display device comprising
an electrostatic discharge circuit comprising diode units comprising a first diode and a second diode,
one of the data lines comprising a first end connected to a node between the first diode and the second diode.
Jeoung43 teaches a display device comprising
an electrostatic discharge circuit comprising diode units comprising a first diode and a second diode (electrostatic discharge circuit 12 comprising diode units D1 and D2 comprising a first diode D1 and a second diode D2-Fig 1);
one of the data lines comprising a first end connected to a node between the first diode and the second diode (one of the data lines DL comprising a first end connected to a node between the first diode D1 and the second diode D2-Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Liu11 in view of Du80, as taught by Jeoung43 for the purpose of preventing static electricity (Jeoung43: [0007]).
Regarding claim 20, Liu11, Du80, and Jeoung43 combination discloses all the elements of claim 19, as noted above.
Du80 further teaches a display device further comprising:
a first connection line connected between the first line and the electrostatic discharge circuit beneath the first line (first/top connection line 61 on T3 connected between first line 51 and electrostatic discharge circuit 43 beneath the first line 51-Fig 7, [0066] L 49-55, Fig 10); and
a second connection line connected between the second line and the electrostatic discharge circuit beneath the second line (Second/bottom connection line 61/33 of T6 between the second line 52 and the electrostatic discharge circuit 43 under the second line 52, all the lines being on the same level than G31 so on the substrate 1-Fig 7, [0066] L 49-55, Fig 8, Fig 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitance device of Liu11 in view of Jeoung43, as taught by Du80 for the purpose of improving a product yield of the OLED display apparatus (Du80: [0004]).
Allowable Subject Matter
Claims 12-15 are allowed.
The following is a statement of reasons for the indication of allowance:
Regarding claim 12, the prior art of record does not teach or suggest a display device, namely “a second gate conductive layer above an insulating layer covering the first gate conductive layer; and a source-drain conductive layer above an insulating layer covering the second gate conductive layer, and comprising the source electrode and the drain electrode”.
References such as Du et al. (US20220115280A1-Du80), Jeoung et al. (US 20050243043 A1-Jeoung43), Koo et al. (US20130050173A1-Koo73), Liu et al. (US20210335984A1-Liu84) and Choi et al. (KR102493129B1 from IDS with machine translation-Choi29) combination, teaches a display device, but does not teach or suggest a display device, namely “a second gate conductive layer above an insulating layer covering the first gate conductive layer; and a source-drain conductive layer above an insulating layer covering the second gate conductive layer, and comprising the source electrode and the drain electrode“, in combination with other claimed elements.
The balance of the claims are allowable for at least the above-stated reasons.
Response to Arguments
Applicant’s arguments see pages 8-11 of Remarks, filed on 08/04/2026 with respect to the Claim 12 have been fully considered and are persuasive.
Therefore claim 12 is allowed, and claims 13-15 are allowed at least for their dependencies.
Applicant’s arguments see pages 8-11 of Remarks, filed on 08/04/2026 with respect to the 35 U.S.C 102 rejection of claim 1 and the 35 U.S.C 103 rejection of claim 19 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Claim(s) 1-2 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US20220115280A1-Du80) in view of Jeoung et al. (US 20050243043 A1-Jeoung43), as noted above.
Therefore, claim(s) 1-2 and 16-18 stand rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US20220115280A1-Du80) in view of Jeoung et al. (US 20050243043 A1-Jeoung43).
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US20220115280A1-Du80) in view of Jeoung et al. (US 20050243043 A1-Jeoung43), and further in view of Koo et al. (US20130050173A1-Koo73), as noted above.
Therefore, claim(s) 4-6 stand rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US20220115280A1-Du80) in view of Jeoung et al. (US 20050243043 A1-Jeoung43), and further in view of Koo et al. (US20130050173A1-Koo73).
Claim(s) 7-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US20220115280A1-Du80) in view of Jeoung et al. (US 20050243043 A1-Jeoung43), in view of Koo et al. (US20130050173A1-Koo73), and further in view of Liu et al. (US20210335984A1-Liu84), as noted above
Therefore, claim(s) 7-11 stand rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US20220115280A1-Du80) in view of Jeoung et al. (US 20050243043 A1-Jeoung43), in view of Koo et al. (US20130050173A1-Koo73), and further in view of Liu et al. (US20210335984A1-Liu84).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US20250293511A1-Liu11) in view of Du et al. (US20220115280A1-Du80), and further in view of Jeoung et al. (US 20050243043 A1-Jeoung43), as noted above.
Therefore, claim(s) 19-20 stand rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US20250293511A1-Liu11) in view of Du et al. (US20220115280A1-Du80), and further in view of Jeoung et al. (US 20050243043 A1-Jeoung43).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 09/09/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights