DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species 1 in the reply filed on 16 June 2026 is acknowledged. The traversal is on the ground(s) that Species 2-4 are drawn to the same fabrication method. This is found persuasive. However, since the fabrication process of Figures 17A-19D are disclosed as mutually exclusive with the other listed Species, Species 2-4 together are still a valid species. Thus, the Species Election should have been between the listed Species 1, Species 2-4 as one Species, Species 5, Species 6, Species 7, Species 8, and Species 9 as outlined in the Restriction/Election Requirement of 22 May 2026, and Applicant’s election of Group I and Species 1 still stands. Claims 1-5,7,9,12-16 and 21-28 are drawn to the elected invention/species and are examined. The species election and restriction requirement is deemed proper and is therefore made final.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the inner spacer configuration of claim 15 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 7, 9, 12-14, 16, 21-26 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2022/0328641), Lin et al. (“Lin” US 2023/0180451, and Bae (US 2025/0183098).
Regarding claim 1, Liaw discloses a method of forming a semiconductor structure (Figures 2A-3I), comprising:
forming a first fin structure (left, Figure 3D) and a second fin (right, Figure 3D) structure in a first region (202) and a second region (222) of a substrate (242, see Figure 3B-3D), respectively, wherein each of the first fin structure and the second fin structure comprises first semiconductor layers (302/304) and second semiconductor layers (248/268) alternately stacked (see Figure 3B);
forming a first source/drain feature (208, left in Figure 3D) and a second source/drain feature (208, right in Figure 3D) in the first fin structure (see Figure 3D), and forming a third source/drain feature (228, left in Figure 3D) and a fourth source/drain feature (228, right in Figure 3D) in the second fin structure (see Figure 3D);
forming a first gate structure (310) between the first source/drain feature and the second source/drain feature (208, see Figure 3E) to wrap around each of the second semiconductor layers (248/268) in the first fin structure, and forming a second gate structure (312) between the third source/drain feature and the fourth source/drain feature (228, see Figure 3E) to wrap around each of the second semiconductor layers (248/268) in the second fin structure (see Figure 3E);
forming a first trench over and exposing the first source/drain feature (208, see Figure 3G, para. [0085] where the dielectric layer 250 is first formed and then recessed to expose the source/drain features), and forming a second trench over and exposing the third source/drain feature (228, see Figure 3G, para. [0085] where the dielectric layer 270 is first formed and then recessed to expose the source/drain features); and
depositing a conductive material (256/276) in the first trench and the second trench (see Figure 3H) to form a first source/drain contact (256) and a second source/drain contact (276, see Figure 3H).
Liaw does not teach:
forming a hard mask layer in the first region of the substrate to cover a surface of the first trench;
etching the third source/drain feature to extend the second trench in a Z-direction;
removing the hard mask layer; and
depositing a conductive material in the first trench and the second trench to form a first source/drain contact and a second source/drain contact.
Lin teaches, however:
Forming a hard mask layer in the first region of the substrate (162, see Figure 5J-1);
etching the third source/drain feature (124a) to extend the second trench in a Z-direction (see Figure 5J-1);
removing the hard mask layer (162); and
depositing a conductive material (174) in the first trench and the second trench to form a first source/drain contact and a second source/drain contact (see Figure 5N-1).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Lin into the teachings of Liaw to extend the second trench in order to increase contact area between the source/drain feature and the source/drain contact (Lin, para. [0146]).
The combination of Liaw and Lin does not teach the process of forming a hard mask layer in the first region of the substrate to cover a surface of the first trench and then etching the third source/drain feature to extend the second trench vertically. Rather, one trench is fully etched at a time while the other trenches are covered with an etch mask (see Lin).
Bae teaches such a process of forming trenches for contact plugs, where a preliminary etch is performed on two trenches (Figure 5, 63T and 62T) in two regions of a substrate, and subsequently an etch mask is formed to fully cover only one of the trenches (67, Figure 7), in order to further etch the other trench (62T, Figure 8).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Bae into the teachings of Liaw and Lin to include a preliminary etch for both trenches and a secondary etch of only one trench while masking the other. One having ordinary skill in the art would have recognized that the manufacturing process would be streamlined by performing a preliminary etch on all trenches and then using masks to cover trenches that do not need to be etched further, thereby reducing the number of processing or etching steps, as well as fewer masks separately patterned and used to form the trenches of different depths. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 2, While Bae does not explicitly teach a photolithography process of forming the hard mask pattern Lin discloses such a process, forming a hard mask material layer (158) in the first region and the second region (to form openings, para. [0126]);
forming a photoresist layer on the hard mask material layer in the first region (para. [0126]); and
removing the hard mask material layer from the second region to form the hard mask layer in the first region, such that the first trench is covered by the hard mask layer and the third source/drain feature is exposed by the second trench (see para. [0126]).
It would have been obvious to incorporate the photolithography teachings of Lin into the combinations of other teachings for the purpose of utilizing a method with higher precision and scalability.
Regarding claim 4, Lin teaches forming a contact etch stop layer (132) on the first source/drain feature, the second source/drain feature, the third source/drain feature, and the fourth source/drain feature (see Figure 5C-2), and forming an interlayer dielectric (ILD) layer (134) on the contact etch stop layer (132),
wherein the forming of the first trench and the second trench is performed by etching through the contact etch stop layer (132) and the ILD layer (134, see Figures 5J-1, 5L-1).
It would have been obvious to a person having ordinary skill in the art to incorporate the CESL and ILD as taught by Lin into the teachings of claim 1 for the purpose of filling the space between dummy gates (Lin, para. [0088]).
Regarding claim 5, the combination of Lin, Liaw, and Bae teach the limitations of claim 5:
Liaw discloses wherein a first width (W1) of the first source/drain feature (208, left) is smaller than a second width (W5) of the third source/drain feature (228, left) in an X-direction (horizontal direction in Figure 3H, see para. [0098]); and
Lin and Bae teach, incorporated into the teachings of Liaw, wherein after the extending of the second trench, a second depth of the second trench is greater than a first depth of the first trench in the Z-direction (see Lin, Figure 5L-1, Bae Figure 8, incorporated into the first and second trenches of Lin which later form the source/drain features).
Regarding claim 7, forming a first dummy gate structure and a second dummy gate structure on the first fin structure and the second fin structure (not shown explicitly in the Figures, but disclosed in para. [0082], which describes dummy gates may be disposed in the gate regions 310/312 before removal of layers 302/304), respectively;
forming source/drain trenches (para. [0080]) on opposite sides of the first dummy gate structure and on opposite sides of the second dummy gate structure (para. [0082]); and
forming the first source/drain feature (208, left), the second source/drain feature (208, right), the third source/drain feature (228, left), and the fourth source/drain feature (228, right) in the source/drain trenches (para. [0080]).
Regarding claim 9, Liaw discloses a method of forming a semiconductor structure (Figures 2A-3I), comprising:
forming first semiconductor layers (302/304) and second semiconductor layers (248/268) over a substrate (242), wherein the first semiconductor layers (302/304) and the second semiconductor layers (248/268) are alternately stacked in a Z- direction (see Figure 3B);
patterning the first semiconductor layers (302/304) and the second semiconductor layers (248/268) to form a first fin structure and a second fin structure (see Figure 3D);
forming a first source/drain feature (208, left) and a second source/drain feature (208, right) in the first fin structure (Figure 3D) that are spaced apart from each other in an X-direction (horizontal direction in Figure 3D), and forming a third source/drain feature (228, left) and a fourth source/drain feature (228, right) in the second fin structure (Figure 3D) that are spaced apart from each other in the X-direction (horizontal direction in Figure 3D);
forming a first gate structure (310) between the first source/drain feature and the second source/drain feature (208, see Figure 3E) and a second gate structure (312) between the third source/drain feature and the fourth source/drain feature (228, see Figure 3E);
forming a first trench over and exposing the first source/drain feature (208, see Figure 3G, para. [0085] where the dielectric layer 250 is first formed and then recessed to expose the source/drain features), and forming a second trench over and exposing the third source/drain feature (228, see Figure 3G, para. [0085] where the dielectric layer 270 is first formed and then recessed to expose the source/drain features); and
depositing a conductive material (256/276) in the first trench and the second trench (see Figure 3H) to form a first source/drain contact (256) and a second source/drain contact (276, see Figure 3H).
Liaw does not teach:
forming a hard mask layer in the first trench and the second trench;
removing a second portion of the hard mask layer formed in the second trench;
etching the third source/drain feature to extend the second trench in a Z-direction;
removing the hard mask layer; and
depositing a conductive material in the first trench and the second trench to form a first source/drain contact and a second source/drain contact.
Lin teaches, however:
Forming a hard mask layer in the first region of the substrate (162, see Figure 5J-1);
etching the third source/drain feature (124a) to extend the second trench in a Z-direction (see Figure 5J-1);
removing the hard mask layer (162); and
depositing a conductive material (174) in the first trench and the second trench to form a first source/drain contact and a second source/drain contact (see Figure 5N-1).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Lin into the teachings of Liaw to extend the second trench in order to increase contact area between the source/drain feature and the source/drain contact (Lin, para. [0146]).
The combination of Liaw and Lin does not teach the process of forming a hard mask layer in the first trench and second trench, removing a second portion of the hard mask layer formed in the second trench, and etching the third source/drain feature to extend the second trench vertically. Rather, one trench is fully etched at a time while the other trenches are covered with an etch mask (see Lin).
Bae teaches such a process of forming trenches for contact plugs, where a hard mask layer (65L) in the first trench and the second trench (63T, 62T, see Figure 6), and removing a second portion of the hard mask layer formed in the second trench (62T, see Figure 7 shows portion 66 of the mask remaining after partial removal), and etching the second trench (62T) to extend the second trench in a Z-direction (see Figure 8).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Bae into the teachings of Liaw and Lin to include a preliminary etch for both trenches and a secondary etch of only one trench while masking the other. One having ordinary skill in the art would have recognized that the manufacturing process would be streamlined by performing a preliminary etch on all trenches and then using masks to cover trenches that do not need to be etched further, thereby reducing the number of processing or etching steps, as well as fewer masks separately patterned and used to form the trenches of different depths. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 12, Liaw discloses wherein a first width (W3) of the first trench is smaller than a second width (W7) of the second trench in the X-direction (horizontal direction, see Figure 3H, para. [0099]); and
wherein a first distance between a middle line of the first source/drain feature (208, left) and a middle line of the second source/drain feature (208, right) is smaller than a second distance between a middle line of the third source/drain feature (228, left) and a middle line of the fourth source/drain feature (228, right) in the X-direction (horizontal direction, see Figure 3H).
Regarding claim 13, the combination of Liaw, Lin, and Bae teaches wherein after the extending of the second trench, a second depth of the second trench is greater than a first depth of the first trench in the Z-direction (see Lin, Figure 5M-3), wherein the second depth (D1) is at least 4 nanometers greater than the first depth (D2, see para. [0150]-[0151], which discloses a range of depths overlapping the claimed range of difference of depths).
Regarding claim 14, Liaw discloses wherein the forming of the first gate structure (310) comprises:
removing the first semiconductor layers (302) in the first fin structure to form a first gate trench (para. [0082]);
and forming the first gate structure (310) in the first gate trench to wrap around each of the second semiconductor layers (248) in the first fin structure (see Figure 3E).
Regarding claim 16, the combination of Liaw, Lin, and Bae teaches the limitations of claim 16:
Liaw discloses forming a first silicide (254) on a surface of the first source/drain feature exposed by the first trench (para. [0040]);
And after the extending of the second trench (as taught by Lin and Bae), forming a second silicide layer (172 of Lin, 274 of Liaw) on a surface of the third source/drain feature exposed by the second trench (see Figure 5N-1 of Lin, Figure 3H of Liaw).
Regarding claim 21, Liaw discloses a method of forming a semiconductor structure (Figures 2A-3I), comprising:
forming a first fin structure (left, Figure 3D) and a second fin (right, Figure 3D) structure in a first region (202) and a second region (222) of a substrate (242, see Figure 3B-3D), respectively, wherein each of the first fin structure and the second fin structure comprises first semiconductor layers (302/304) and second semiconductor layers (248/268) alternately stacked (see Figure 3B);
forming a first dummy gate structure and a second dummy gate structure on the first fin structure and the second fin structure (not shown explicitly in the Figures, but disclosed in para. [0082], which describes dummy gates may be disposed in the gate regions 310/312 before removal of layers 302/304), respectively;
forming a first source/drain feature (208, left) and a second source/drain feature (208, right) on opposite sides of the first dummy gate structure (para. [0082]) in a first direction (horizontal direction in Figure 3D), and forming a third source/drain feature (228, left) and a fourth source/drain feature (228, right) on opposite sides of the second dummy gate structure (para. [0082]) in the first direction; and
forming a first trench over and exposing the first source/drain feature (208, see Figure 3G, para. [0085] where the dielectric layer 250 is first formed and then recessed to expose the source/drain features), and forming a second trench over and exposing the third source/drain feature (228, see Figure 3G, para. [0085] where the dielectric layer 270 is first formed and then recessed to expose the source/drain features).
Liaw does not teach:
forming a hard mask layer in the first region and the second region;
removing a second portion of the hard mask layer formed in the second region to expose the second trench, wherein the first trench is covered by a first portion of the hard mask layer formed in the first region;
etching the third source/drain feature to extend the second trench in a vertical direction; and
removing the first portion of the hard mask layer formed in the first region.
Lin teaches, however:
Forming a hard mask layer in the first region of the substrate (162, see Figure 5J-1);
etching the third source/drain feature (124a) to extend the second trench in a Z-direction (see Figure 5J-1);
removing the hard mask layer (162); and
depositing a conductive material (174) in the first trench and the second trench to form a first source/drain contact and a second source/drain contact (see Figure 5N-1).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Lin into the teachings of Liaw to extend the second trench in order to increase contact area between the source/drain feature and the source/drain contact (Lin, para. [0146]).
The combination of Liaw and Lin does not teach the process of forming a hard mask layer in the first region and second region, removing a portion of the hard mask layer in the second region to expose the second trench, while the hard mask layer is still covering the first trench of the first region, and etching the third source/drain feature to extend the second trench vertically. Rather, one trench is fully etched at a time while the other trenches are covered with an etch mask (see Lin).
Bae teaches such a process of forming trenches for contact plugs, where a hard mask layer (65L) in the first region and the second region (regions occupied by 63T, 62T, see Figure 6), and removing a portion of the hard mask layer formed in the second region to expose the second trench (62T, see Figure 7 shows portion 66 of the mask remaining after partial removal), wherein the first trench (63T) is covered by a first portion of the hard mask layer (67, see Figure 7), and etching the second trench (62T) to extend the second trench in a Z-direction (see Figure 8).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Bae into the teachings of Liaw and Lin to include a preliminary etch for both trenches and a secondary etch of only one trench while masking the other. One having ordinary skill in the art would have recognized that the manufacturing process would be streamlined by performing a preliminary etch on all trenches and then using masks to cover trenches that do not need to be etched further, thereby reducing the number of processing or etching steps, as well as fewer masks separately patterned and used to form the trenches of different depths. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 22, while Bae does not explicitly teach a photolithography process of forming the hard mask pattern, Lin discloses such a process, where forming a photoresist layer in the first region and the second region (to form openings, para. [0126]);
patterning the photoresist layer to remove a portion of the photoresist layer from the second region, such that a remaining portion of the photoresist layer remains in the first region (para. [0126]), wherein the first trench is covered by the first portion of the hard mask layer (158) and the remaining portion of the photoresist layer (para. [0126]); and
after the patterning of the photoresist layer, performing an etching process to etch the third source/drain feature to extend the second trench (Lin teaches etching the trench in the patterned opening, Bae teaches further etching the trench to extend the trench).
It would have been obvious to incorporate the photolithography teachings of Lin into the combinations of other teachings for the purpose of utilizing a method with higher precision and scalability.
Regarding claim 23, Liaw discloses wherein a first width (W1) of the first source/drain feature (208, left) is smaller than a second width (W5) of the third source/drain feature (228, left) in the first direction (horizontal direction in Figure 3D, para. [0098]); and
Lin and Bae teach, incorporated into the teachings of Liaw, wherein after the extending of the second trench, a second depth of the second trench is greater than a first depth of the first trench in the vertical direction (see Lin, Figure 5L-1, Bae Figure 8, incorporated into the first and second trenches of Lin which later form the source/drain features).
Regarding claim 24, Liaw discloses wherein a first distance between a middle line of the first source/drain feature (208, left) and a middle line of the second source/drain feature (208, right) is smaller than a second distance between a middle line of the third source/drain feature (228, left) and a middle line of the fourth source/drain feature (228, right) in the first direction (horizontal direction, see Figure 3H).
Regarding claim 25, Liaw further discloses forming source/drain trenches (para. [0080]) on opposite sides of the first dummy gate structure and on opposite sides of the second dummy gate structure (para. [0082]) in the first direction; and
forming the first source/drain feature (208, left), the second source/drain feature (208, right), the third source/drain feature (228, left), and the fourth source/drain feature (228, right) in the source/drain trenches (para. [0080]).
Regarding claim 26, Liaw further discloses partially recessing the first semiconductor layers (302/304) through the source/drain trenches to form inner spacer recesses (para. [0081]) between the second semiconductor layers (248/268) in the vertical direction (see Figure 3D); and
forming inner spacers (para. [0082]) in the inner spacer recesses (see Figure 3D).
Regarding claim 28, Bae discloses wherein the first portion of the hard mask layer is in form of a layer (67, see Figure 7).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw, Lin, and Bae as applied to claim 1 above, and further in view of Jao et al. (“Jao” US 2023/0039440).
Regarding claim 3, Liaw and Lin do not disclose forming a dielectric layer in the first trench and the second trench; and
removing horizontal portions of the dielectric layer to form sidewall dielectric layers on sidewalls of the first trench and the second trench.
Jao discloses a dielectric layer (158, Figure 2V) in a source/drain contact trench (210); and
removing horizontal portions of the dielectric layer (542) to form sidewall dielectric layers (para. [0079]) on sidewalls of trenches (see Figure 3).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Jao into the teachings of Liaw, Lin, and Bae to include the dielectric layer as claimed for the purpose of reducing parasitic capacitance between the gate and source/drain contacts (Jao, para. [0122]).
Claims 15 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw, Lin, and Bae as applied to claims 14 and 26, respectively, above, and further in view of Yu et al. (“Yu” US 2025/0227946).
Regarding claim 15, Liaw does not teach specific widths of the inner spacers.
Yu teaches:
wherein the first gate structure comprises a first inner portion (151) and a second inner portion (152, Figure 3B);
wherein the first inner portion (151) is between a topmost one of the second semiconductor layers (141) and a second topmost one of the second semiconductor layers (142) in the first fin structure (see Figure 3B), and the second inner portion (152) is between the second topmost one of the second semiconductor layers (142) and a third topmost one of the second semiconductor layers (143) in the first fin structure (see Figure 3B); and
wherein a first length (U1) of the first inner portion (151) is smaller than a second length (U2) of the second inner portion (152) in the X-direction (horizontal direction in Figure 3B, see para. [0050]).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of the inner portions of Yu into the teachings of Liaw, Lin, and Bae. Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See MPEP 2144.04(IV)(A).
Regarding claim 27, Liaw does not teach specific widths of the inner spacers.
Yu teaches:
wherein in the first fin structure, the inner spacers (151-153) comprise first inner spacers (151) and second inner spacers (152, Figure 3A);
wherein the first inner spacers (151) are formed between a topmost one of the second semiconductor layers (141) and a second topmost one of the second semiconductor layers (142) in the first fin structure, and the second inner spacers (152) are formed between the second topmost one of the second semiconductor layers (142) and a third topmost one of the second semiconductor layers (142) in the first fin structure (see Figure 3A); and
wherein a first thickness (T1) of the first inner spacers is greater than a second thickness (T2) of the second inner spacers in the first direction (horizontal direction in Figure 3A).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of the inner portions of Yu into the teachings of Liaw, Lin, and Bae. Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See MPEP 2144.04(IV)(A).
Conclusion
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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