CTNF 18/635,461 CTNF 84562 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Claims 1-20 are presented for examination. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 3 and 4 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee et al. (US Pub. No. 2018/0182860 A1), hereafter referred to as Lee . As to claim 1, Lee discloses a device (fig 7), comprising: a substrate (12); a ferroelectric layer (FE layer 20) disposed over the substrate (12) in a cross-sectional side view (fig 7 is cross-sectional view); a gate dielectric layer (50) disposed over the ferroelectric layer (20) in the cross-sectional side view (fig 7); a gate electrode layer (gate electrode 48) disposed over the gate dielectric layer (50) in the cross-sectional side view (fig 7); and an interlayer dielectric (30) disposed over the ferroelectric layer (20) in the cross-sectional side view (fig 7). As to claim 3, Lee discloses the device of claim 1 (paragraphs above), a conductive structure (34) disposed over the ferroelectric layer (20) in the cross-sectional side view (fig 7), wherein the conductive structure (34) extends vertically through the ILD (30). As to claim 4, Lee discloses the device of claim 1 (paragraphs above), wherein the ferroelectric layer contains hafnium oxide, hafnium zirconium oxide, hafnium aluminum oxide, lead zirconium titanium oxide, or barium titanium oxide ([0038]) . 07-15-aia AIA Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chang et al. (US Pub. No. 2018/0151745 A1), hereafter referred to as Chang . As to claim 18, Chang discloses a device (fig 17A-B), comprising: a substrate (10); a channel (24) disposed over the substrate (10) in a cross-sectional side view; a gate structure (gate structure 115 in FET region shown in fig 17A) disposed over the channel (24) in the cross-sectional side view; an isolation structure (30) disposed adjacent to the substrate (1) in the cross-sectional side view; a first conductive electrode (electrode 115 in NC-FET region shown in fig 17A) disposed over the isolation structure (3) in the cross-sectional side view; a ferroelectric layer (120) disposed over the first conductive electrode (115 in NC-FET region) in the cross-sectional side view; and a second conductive electrode (130) disposed over the ferroelectric layer (120) in the cross-sectional side view. As to claim 20, Chang discloses the device of claim 18 (paragraphs above), a source/drain region (60) disposed between the channel (24) and the isolation structure (30) . 07-15-aia AIA Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ota et al. (US Pub. No. 2020/0243687 A1), hereafter referred to as Ota . As to claim 18, Ota discloses a device (fig 14), comprising: a substrate (SB); a channel (FA) disposed over the substrate (SB) in a cross-sectional side view; a gate structure (GE2) disposed over the channel (FA) in the cross-sectional side view; an isolation structure (EI) disposed adjacent to the substrate (SB) in the cross-sectional side view; a first conductive electrode (PG1) disposed over the isolation structure (EI) in the cross-sectional side view; a ferroelectric layer (FR) disposed over the first conductive electrode (PG1) in the cross-sectional side view; and a second conductive electrode (PG2) disposed over the ferroelectric layer (FR) in the cross-sectional side view. As to claim 19, Chang discloses the device of claim 18 (paragraphs above), wherein the first conductive electrode (PG1) is electrically coupled to the gate structure (GE2) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 1, 3-5, 8-9 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Flachowsky et al. (US Pub. No. 2016/0358915 A1), hereafter referred to as Flachowsky in view of Ota . As to claim 1, Flachowsky discloses a device (fig 1F, comprising: a substrate (1); a ferroelectric layer (26) disposed over the substrate (1) in a cross-sectional side view (fig 1F); a gate dielectric layer (52) disposed over the ferroelectric layer (26) in the cross-sectional side view (fig 1F); a gate electrode layer ([0046]) disposed over the gate dielectric layer (52) in the cross-sectional side view (fig 1F). Flachowsky does not disclose an interlayer dielectric (ILD) disposed over the ferroelectric layer in the cross-sectional side view. Nonetheless, Ota discloses an interlayer dielectric (IL2) disposed over a ferroelectric layer (FR) in a cross-sectional side view (fig 18). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form an interlayer dielectric over the ferroelectric layer of Flachowsky as taught by Ota since this allows for electrical interconnection of the semiconductor elements. As to claim 3, Flachowsky in view of Ota discloses the device of claim 1 (paragraphs above). Ota further discloses a conductive structure(plug PG2) disposed over the ferroelectric layer (FR) in the cross-sectional side view, wherein the conductive structure extends vertically through the ILD (IL2). As to claim 4, Flachowsky in view of Ota discloses the device of claim 1 (paragraphs above). Flachowsky further discloses wherein the ferroelectric layer contains hafnium oxide, hafnium zirconium oxide, hafnium aluminum oxide, lead zirconium titanium oxide, or barium titanium oxide ([0049]). As to claim 5, Flachowsky in view of Ota discloses the device of claim 1 (paragraphs above). Flachowsky further discloses a dielectric structure (sidewall structure of 52) disposed over the substrate (1) in the cross-sectional side view (fig 1F), wherein a side surface of the ferroelectric layer (26) is in direct contact with the dielectric structure (sidewall structure of 52). As to claim 8, Flachowsky in view of Ota discloses the device of claim 1 (paragraphs above). Flachowsky further discloses wherein the cross-sectional side view is a first cross-sectional side view taken along a vertical direction and a first horizontal direction, and wherein in a second cross-sectional side view taken along the vertical direction and a second horizontal direction different from the first horizontal direction: the gate dielectric layer (52) partially wraps around a portion of the ferroelectric layer (26); and the gate electrode layer partially wraps around a portion of the gate dielectric layer ([0046]). As to claim 9, Flachowsky in view of Ota discloses the device of claim 8 (paragraphs above). Flachowsky further discloses a semiconductor fin (32) structure that protrudes out of the substrate (1) in the vertical direction, wherein the ferroelectric layer (26) is separated from the semiconductor fin structure (32) in the second horizontal direction. As to claim 12, Flachowsky discloses a device (fig 1F), comprising: a substrate (1); a ferroelectric layer (26) disposed over the substrate (1) in both a first cross-sectional side view defined by a first horizontal direction and a vertical direction and a second cross-sectional side view defined by a second horizontal direction and the vertical direction; a semiconductor fin structure (32) that protrudes vertically out of the substrate (1) in the vertical direction, wherein the semiconductor fin structure (32) and the ferroelectric layer (26) are spaced apart from one another in the second horizontal direction; a gate dielectric layer (52) disposed over the ferroelectric layer (26) in the first cross-sectional side view and partially wrapping around the semiconductor fin structure (32) and the ferroelectric layer (26) in the second cross-sectional side view; and a gate electrode layer disposed over the gate dielectric layer ([0046]). However, Flachowsky does not explicitly show the gate electrode layer. Nonetheless, Ota discloses a gate electrode layer (fig 14, GE2) over a gate dielectric layer (GI) of a fin structure (FA) and wrapping around a gate dielectric layer (GI), wherein a portion of the gate electrode layer (GE2) is disposed between a ferroelectric layer (FR) and a semiconductor fin (FA). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the gate electrode of Flachowsky to be located over and wrapping around the gate dielectric as taught by Ota since this will decrease short channel effects of the semiconductor device. As to claim 13, Flachowsky in view of Ota disclose the device of claim 12 (paragraphs above). Flachowsky does not disclose an ILD. Ota further discloses an interlayer dielectric (IL2) disposed over the ferroelectric layer (FR) in the first cross-sectional side view; and a conductive structure (plug PG2) that extends through the ILD (IL2) in the vertical direction in the first cross-sectional side view, wherein the conductive structure (PG2) is electrically coupled to the ferroelectric layer (FR). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form an interlayer dielectric over the ferroelectric layer of Flachowsky as taught by Ota since this allows for electrical interconnection of the semiconductor elements . 07-21-aia AIA Claim (s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Flachowsky in view of Ota and further in view of Kim et al. (US Pub. No. 2020/0013899 A1), hereafter referred to as Kim . As to claim 2, Flachowsky in view of Ota discloses the device of claim 1 (paragraphs above). Flachowsky in view of Ota a gate spacer disposed between the gate electrode and the ILD in the cross-sectional side view. Nonetheless, Kim discloses a gate spacer (fig 2A, GS) disposed between a gate electrode (GE) and an ILD (110) in a cross-sectional side view (fig 2A). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a gate spacer in the device of Flachowsky in view of Ota as taught by Kim since this will provide improved separation between the source/drain regions from the gate electrode . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 6-7, 10-11 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest wherein the dielectric structure extends vertically partially through the ILD, as recited in claim 6; wherein a side surface of the gate electrode or a side surface of the gate dielectric are in direct contact with the dielectric structure, as recited in claim 7; an interfacial layer that is disposed over the semiconductor fin structure but not over the ferroelectric layer, as recited in claim 10; a liner layer that is in direct contact with a bottom surface of the ferroelectric layer and with a portion of a side surface of the semiconductor fin structure, as recited in claim 11; an interfacial layer that is disposed between the gate dielectric layer and the semiconductor fin structure in the second cross-sectional side view, wherein no portion of the interfacial layer is disposed between the gate dielectric layer and the ferroelectric layer in the second cross-sectional side view, as recited in claim 14; or a mask layer disposed between the ferroelectric layer and the semiconductor fin structure in the second cross-sectional side view, as recited in claim 15. Claims 16-17 are allowable because of their dependence from an allowable claim . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 6/12/2026 Application/Control Number: 18/635,461 Page 2 Art Unit: 2893 Application/Control Number: 18/635,461 Page 4 Art Unit: 2893 Application/Control Number: 18/635,461 Page 5 Art Unit: 2893 Application/Control Number: 18/635,461 Page 6 Art Unit: 2893 Application/Control Number: 18/635,461 Page 7 Art Unit: 2893 Application/Control Number: 18/635,461 Page 8 Art Unit: 2893 Application/Control Number: 18/635,461 Page 9 Art Unit: 2893 Application/Control Number: 18/635,461 Page 10 Art Unit: 2893 Application/Control Number: 18/635,461 Page 11 Art Unit: 2893 Application/Control Number: 18/635,461 Page 12 Art Unit: 2893 Application/Control Number: 18/635,461 Page 13 Art Unit: 2893 Application/Control Number: 18/635,461 Page 14 Art Unit: 2893
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