Attorney’s Docket Number: GF2023228-US-NP
Filing Date: 04/15/2024
Claimed Priority Date: N/A
Applicants: Gedela et al.
Examiner: Aneesa Baig
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
In [0021], “Although not shown, the airgaps 50, 60 may also be provided in the top substrate 50 in any combination as described herein” Top substrate 50 is missing from the drawings. Examiner assumes this statement should be corrected to “top substrate 30.”
Drawings
The drawings of Figure 2 are objected to under 37 CFR 1.83(a) because they fail to show an airgap feature as described in the specification. It appears in Figure 2 there are oval shaped air gaps above transistors 14a and 14b but they are missing a label, and rather, the airgaps 50 and 60 are contained the inside bottom substrate 40 layers which are made of semiconductor and insulator SOI layers, not air gaps. Further, the paragraph [0021] describes the airgaps formed over the substrate 40, not within. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing (MPEP § 608.02(d), and applicant is encouraged to review incorrect labelling and descriptions in the remainder of the disclosure not identified above.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
As MPEP 2173.02, states, claims 1-20 are viewed in the light of the specification. Claim 1 recites “A structure comprising: a top substrate comprising at least one top transistor and metal wiring structures; and a bottom substrate comprising at least one bottom transistor and metal wiring structures. ” However, in Figure 2, the top substrate 30 and bottom substrate 40 are made of SOI technology ([0016]) and do not contain the transistors or the metal wiring structures. Further, [0018] describes “For the top circuit 12, the plurality of transistors 12a, 12b, 12c, 12n are formed in series on the top semiconductor layer 30c. Similarly, for the bottom circuit 14, the plurality of transistors 14a, 14b, 14c, 14n are formed in series on the bottom semiconductor layer 40c”. Therefore, it is unclear according to the specification if the top and bottom substrate comprise any transistors or metal wirings, thus rendering the claim indefinite. For the purpose of examination, the claims will be construed as reciting -- A structure comprising: a top circuit comprising at least one top transistor and metal wiring structures; and a bottom circuit comprising at least one bottom transistor and metal wiring structures --, as best understood by the examiner in view of the original disclosure, until further clarifications are provided by the applicant.
Claims 2-12 depend from claim 1, thus inherit the deficiencies identified supra, all instances of top substrate and bottom substrate will be understood by the examiner as top circuit and bottom circuit.
Regarding Claim 13, claim 13 recites “A structure comprising: a top substrate comprising a plurality of top transistors in series” and then also recites “a bottom substrate comprising a plurality of bottom transistors in series.” Se explanation from above in paragraph 5. Examiner understands this claim to recite -- A structure comprising: a top circuit comprising a plurality of top transistors in series -- and -- a bottom circuit comprising a plurality of bottom transistors in series--
Regarding Claim 20, see 112 (b) rejection of Claim 1, as it would be considered repeated here.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102 (a)(1) as anticipated by Toya (JP 2015074326 A, Hereinafter Toya).
Regarding Claim 1, Toya (e.g., Figure 11-14, [0001]-[0050][0028]) shows all aspects of the instant invention, including, a structure (switching element unit 1) comprising:
a top circuit (second insulating substrate 12) comprising at least one top transistor (first chip 21 is contained in the substrate 12, containing an IGBT [0014]-[0017]) and metal wiring structures (via 314, via 318, bonding layer 54, 54a, 56, 42,44 ); and
a bottom circuit (13) comprising at least one bottom transistor ( Second chip 22 containing an IGBT [0015]-[0020]) and metal wiring structures (),
the bottom circuit being attached to the top circuit with the at least one top transistor being electrically connected to the at least one bottom transistor (first chip and second chip are connected via first conductor portion 31 and second conductor portion 32 and 51, 52 [0042]) and a portion of the metal wiring structures of the top circuit and a portion of the metal wiring structures of the bottom circuit comprising at least one shared capacitor (capacitor 40 [0036] electrode 42 is connected to 54 and electrode 44 is connected to 55) between the at least one top transistor and the at least one bottom transistor:
Regarding Claim 20, see rejections from Claim 1, as they would be considered repeated here.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Toya in view of Then (US 20230050491 A1, hereinafter Then).
Regarding Claim 2, Toya shows wherein the shared capacitor comprises a capacitor (40 contains a dielectric layer between two metal layers) and the at least one bottom transistor comprises a switch (switching element in the illustrated example was an IGBT [0051]).
While Toya shows a dielectric between the capacitor, it is silent about the specific material used as a dielectric being an oxide.
Then (e.g., abstract [0044]), on the other hand and in a related field of capacitors, teaches a variety of oxide materials that may be used in parallel plate capacitors to replace SiN layer with a higher dielectric constant to achieve high voltage.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a metal oxide metal capacitor in the design of Toya, to achieve high voltage using a higher dielectric constant. Further, MPEP § 2141 provides that an invention may render a claimed limitation obvious when it would be “obvious to try” to choose from a finite number of identified, predictable solutions, with a reasonable expectation of success. In such an instance it would be obvious to try varying dielectric materials with a reasonable expectation of success to adjust capacitance where there are only a finite number of solutions.
Claims 3, 4 are rejected under 35 U.S.C. 103 as being unpatentable over Toya in view of Abdul-Ridha (US 20090065895 A1, hereinafter Abdul).
Regarding claim 3, While Toya shows a dielectric between the capacitor, it is silent about the specific material being a high-k dielectric.
Abdul ([0005]-[0008]), on the other hand and in a related field of capacitors, teaches using a dielectric having a higher dielectric constant than silicon nitride can be utilized to increase the capacitance density of the MIM capacitor.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a high-k dielectric material used in the device of Toya, as taught by Abdul, to increase capacitance density, thereby providing a desired capacitance in a smaller area.
Regarding Claim 4, Toya shows the capacitor (40) is sandwiched between both circuits ([002]).
Claims 7 are rejected under 35 U.S.C. 103 as being unpatentable over Toya in view of Yami et- al (US 10707120 B1, hereinafter Yami).
Regarding Claim 7, while Toya shows transistors in the circuit layers, is does not show air gaps.
Yami (Fig 1, 8 Page 10, Col 2 and 3), on the other hand and in a related field of SOI devices, teaches using air gaps (150A) above the transistor structure to reduce stress and reduction of inter-layer and intra-layer capacitance.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have air gaps in the structure of Toya to improve the rate of performance of RF switches.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANEESA RIAZ BAIG/
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Prosecution Insights