DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/15/2024 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 11,990,377. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 10 of U.S. Patent No. 11,990,377 recites all of the limitations in claim 1 of the instant application.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 11,990,377. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 10 of U.S. Patent No. 11,990,377 recites all of the limitations in claim 2 of the instant application.
Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. 11,990,377. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 7 of U.S. Patent No. 11,990,377 recites all of the limitations in claim 10 of the instant application.
Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 11,990,377. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 15 of U.S. Patent No. 11,990,377 recites all of the limitations in claim 18 of the instant application.
Prior art of record
Re claim 1, Jung et al. (US Pat. 10,658,463) teaches a structure (Figs. 15-17) comprising: a semiconductor substrate (102a); a first plurality of isolation regions (104, “in TR1”) and a second plurality of isolation regions (104, “in TR2”) in the semiconductor substrate (102a); a first strip group comprising a first plurality of semiconductor strips between the first plurality of isolation regions (Fig. 15, “lower portion 102b left of trench TR2”); a second strip group comprising at least one second semiconductor strip between the second plurality of isolation regions (Fig. 15, “lower portion 102b right of trench TR2”), a first epitaxy region (114a, Fig. 16, “left of trench TR2”), wherein the first epitaxy region is joined to the first plurality of semiconductor strips (Fig. 15, “lower portion 102b left of trench TR2”), a second epitaxy region (114a, Fig. 16, “right of trench TR2”) on the second strip group (Fig. 15, “lower portion 102b right of trench TR2”), wherein the second epitaxy region is spaced apart from the first epitaxy region (Fig. 16).
Jung does not explicitly teach wherein the second strip group is immediately neighboring the first strip group; and wherein the first epitaxy region comprises a topmost surface that fits a tangent line in a cross-section of the structure, and wherein a first side of the tangent line closer to the second strip group is lower than a second side of the tangent line farther away from the second strip group.
Re claim 10, Hung et al. (US Pat. 11,037,827) teaches a structure (Fig. 10) comprising: a semiconductor substrate (101); a plurality of epitaxy regions (124) comprising bottoms joined to different portions of the semiconductor substrate (101), wherein the plurality of epitaxy regions are merged to form a first epitaxy region (129, Fig. 10); a first silicide layer (171) over and contacting the first epitaxy region (129), wherein a first top surface of the first silicide layer (171) fits a first tangent line (Fig. 10). Hung does not explicitly teach a second epitaxy region physically separated from the first epitaxy region, wherein portions of the first tangent line closer to the second epitaxy region are lower than portions of the first tangent line farther away from the second epitaxy region; a second silicide layer over and contacting the second epitaxy region; and a contact plug contacting both of the first silicide layer and the second silicide layer. Re claim 18, Tsai et al. (2019/0097051) teaches a structure (Fig. 10) comprising: a plurality of dielectric isolation regions (114); a plurality of semiconductor strips (110) laterally between the plurality of dielectric isolation regions (114); a plurality of semiconductor fins (“lower portion of ‘124”) overlapping the plurality of semiconductor strips (110) and protruding higher than the plurality of dielectric isolation regions (114); a plurality of gate stacks (138) on top surfaces and sidewalls of the plurality of semiconductor fins (“lower portion of ‘124”); a plurality of epitaxy regions (124); a silicide region (216) contacting the top surface of the first epitaxy region (124), wherein the silicide region comprises a top surface (Fig. 2E), and the top surface fits a tangent line (Fig. 2E); and a contact plug (220) over and contacting the silicide region (216).
Tsai does not explicitly teach the plurality of epitaxy regions, each being between, and joining sidewalls of, two of the plurality of semiconductor fins, wherein the plurality of epitaxy regions are merged as a first epitaxy region; a second epitaxy region of an opposite type than the first epitaxy region, wherein the second epitaxy region is electrically connected to the first epitaxy region, and wherein the tangent line is tilted, and includes a first part and a second part farther away from the second epitaxy region than the first part, and the second part is higher than the first part.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not anticipate or make obvious the device of claim 1, including each of the limitations and specifically wherein the second strip group is immediately neighboring the first strip group; and wherein the first epitaxy region comprises a topmost surface that fits a tangent line in a cross-section of the structure, and wherein a first side of the tangent line closer to the second strip group is lower than a second side of the tangent line farther away from the second strip group, for the same reasons as mentioned for claim 1 in the prior art of record above. The prior art of record does not anticipate or make obvious the device of claim 10, including each of the limitations and specifically a second epitaxy region physically separated from the first epitaxy region, wherein portions of the first tangent line closer to the second epitaxy region are lower than portions of the first tangent line farther away from the second epitaxy region; a second silicide layer over and contacting the second epitaxy region; and a contact plug contacting both of the first silicide layer and the second silicide layer, for the same reasons as mentioned for claim 10 in the prior art of record above. The prior art of record does not anticipate or make obvious the device of claim 18, including each of the limitations and specifically the plurality of epitaxy regions, each being between, and joining sidewalls of, two of the plurality of semiconductor fins, wherein the plurality of epitaxy regions are merged as a first epitaxy region; a second epitaxy region of an opposite type than the first epitaxy region, wherein the second epitaxy region is electrically connected to the first epitaxy region, and wherein the tangent line is tilted, and includes a first part and a second part farther away from the second epitaxy region than the first part, and the second part is higher than the first part, for the same reasons as mentioned for claim 18 in the prior art of record above. Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
Prosecution Insights