DETAILED ACTION
Response to Arguments
Applicant's arguments filed 20 July 2026 have been fully considered but they are not persuasive.
Claim interpretation under 35 USC § 112(f):
The claims have been amended to change “device” to “circuit”, therefore failing prong a of the three prong test. The claim interpretation under 35 USC 112(f) has been withdrawn.
Rejections under 35 USC § 112(b):
The amendments have clarified the claims, therefore the rejections are withdrawn. See remarks of 20 July 2026.
Rejections under 35 USC 102: Hasegawa
The remarks take the position that Hasegawa teaches the checksum is calculated by the controller, but does not disclose that a checksum is received by the controller. This has been found unpersuasive. Specifically as indicated on page 11 of the remarks, claim 1 requires “an error detection circuit that receives the first data and the first error detection code from a register of a last stage among the plurality of registers”.
Initially, the first data is interpreted as PTD which is output to the BAA controller 104 from controller 101 ([0082]). 104 then creates serial data s1-s8 based on PDT and outputs to converters 621-628 ([0082]). Paragraph [0105] teaches converters output serial data to output lines to shift registers. In other words the PTD received by BAA includes data from the last shift register. That is, the claim only requires the first data and first error detection code to be from a register of a last stage among the plurality of registers. Since the data ultimately is sent to all registers (including a register of a last stage), the PTD received by 104 is “from” the register because this is the data that is intended after conversion to be applied to the claimed register.
Moreover, the claim does not preclude the receipt of the first error code to be a calculation. By receiving the PTD data ([0082]), the check sum is calculated ([0120]-[0122]). Thus 104 receives or “obtains” the checksum ([0122]) from the registers (including the claimed register) as the data that is used is intended to ultimately be transmitted to the register. For instance D26 in SR2 of fig. 16 is from a last stage register. Fig. 25 shows D26 and paragraph [0122] teaches obtaining checksum CS4 from D26. Therefore, calculation of a checksum is receiving a checksum via the result of the calculation (i.e. solution) and the checksum and PTD data are both from the claimed register as this is where the data is transmitted.
This interpretation may be overcome by more clearly requiring the claimed register to transmit the first data and first error code to the error detection circuit.
Rejections under 35 USC 103:
The remarks take the position that Hasegawa2 also does not teach receipt of an error detection code by circuit 41. This is not persuasive. Paragraph [0041] teaches in a data transfer step 106 blanking control data with an added parity bit (error detection code) is output to the buffer control circuit 130 which is processed in sequence for the group of first buffers 60. That is, the error detection code or parity bit is output to the buffer control circuit 130. Paragraph [0032] recites “the data stored in the first buffer 60 and the second buffers 62 (stored values) are output to the error detection circuit 28”. See also paragraph [0059] which explicitly recites: “error detection circuit 28 reads the stored values in the first buffer 60 and the second buffer 62 in each stage and performs error detection of the blanking control data for each shot by performing the parity check or calculating the checksum.”
That is, Hasegawa clearly indicates the data stored in the buffers are output to the error detection circuit. Since the data output from 28 to buffers 60 has an added parity bit, the same data output from buffers (60/62) to circuit 28 includes the same parity bit. Therefore, Hasegawa clearly teaches this limitation.
The remarks continue by suggesting 28 does not receive error codes and thus cannot generate a detection signal indicating a match or mismatch. This has not been found persuasive. As discussed above, the parity bit is initially transmitted from the circuit 28 to buffer with the blanking control data. Since the data is then output to the error detection circuit 28, the parity bit is also output.
While Hasegawa fails to disclosure the matching/mismatching of the parity bit, this feature was known to either (a) Verheul et al. (USPN 4,698,814) or Satoh et al. as discussed previously.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hasegawa et al. (US pgPub 2017/0243714).
Regarding claim 1, Hasegawa teaches a blanking aperture array (fig. 1, 61) system used in a multi-charged particle beam irradiation apparatus (fig. 1), the blanking aperture array system comprising:
a data output circuit (104) configured to output first data (PDT), which is one of a plurality of control data items used in beam irradiation ([0082]), and a first error detection code for detecting an error in the first data generated from the first data ([0120] 104 calculates checksum of the unit data. Note 104 is configured to or “capable of” output such data by creation of serial data on the basis of image data [0082]);
a shift register (fig. 6, SR1, SR2) that includes a plurality of registers (SR1 and SR2) connected in series (figure 6 shows SR1/SR2 connected in series) and is configured to transfer the first data and the first error detection code that are input from the data output circuit ([0082] and [0120] since 104 calculates checksums and outputs serial data on the basis of PDT, it is capable of or “configured to” output data and checksum to shift registers SR1 and SR2 via 621-624);
a buffer (fig. 6, BF) configured to receive the first data that is output from a first register (SR1/SR2 to respective BF, [0106]), the first register being one of the plurality of registers (any one of SR1/SR2);
an electrode (associated BK with SR1/SR2 and BF) configured to receive a voltage based on the first data that is output from the buffer ([0106]); and
an error detection circuit (portion of 104 which performs steps s102-s105 in figure 24) that:
receives the first data and the first error detection code from a register of a last stage among the plurality of registers ([0122] CS (i.e. checksum or error detection code) including last stage register. The registers include the unit data D1-Dn (i.e. last register as evidenced by figure 15-16 which show SR numerated by unit data D1-Dn). Note: since the checksum is calculated from PDT ([0120]) it also includes first data);
generates a second error detection code (s103) for detecting an error in the first data from the first data received from the register of the last stage (if error exists at CS with last stage register data unit, the error detection algorithm in 104 is configured to detect by comparison see paragraph [0134]); and
generate a detection signal indicating a match if the first error detection code from the register of the last stage ([0135]) and the second error detection code match and indicating a mismatch if the first error detection code from the register of the last stage and the second error detection code do not match ([0134]).
Claim 4 is commensurate in scope and anticipated as discussed herein above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa et al. (US pgPub 20160322196) in view of Platzgummer et al. (US pgPub 2005/0242302) and further in view of (a) Verheul et al. (USPN 4,698,814) or Satoh et al. (USPN 5,866,300).
Regarding claim 1, Hasegawa et al. teach a blanking aperture array system (figures 1 and 4) used in a multi-charged particle beam irradiation apparatus (fig. 1), the blanking aperture array system comprising:
a data output circuit (fig. 1, 130) configured to output first data ([0041] teaches 130 outputs blanking control data to the first stage of the first buffers 60 (fig. 4)), which is one of a plurality of control data items used in beam irradiation ([0041] teaches blanking control data is processed in a sequence for the group of the first buffers), and a first error detection code for detecting an error in the first data generated from the first data ([0041] teaches an error detection symbol such as parity bit is added to the output blanking control data);
a clock (clock CLk0 in figure 4 “blanking control data is successively transferred to the first buffers 60 at subsequent stages on the basis of a clock signal CLK0” [0029] ) that includes a plurality of clock signals connected in series (each node of CLK0 to respective buffer 60 ) and is configured to transfer the first data and the first error detection code that are input from the data output circuit ([0029] “blanking control data is successively transferred to the first buffers 60 at subsequent stages on the basis of a clock signal CLK0”. That is, since the blanking control data includes both the blanking signals and the error detection signal output from deflection control circuit 130 ([0041]) and the output is based on the clock CLK0, the clock (i.e. register), transfers the data from the deflection control circuit by clock. See also paragraph [0041] which recites “the deflection control circuit 130 outputs the clock signals CLK0 to CLK3 for data transfer”);
a buffer (60) configured to receive the first data that is output from a first clock ([0042] “the first buffer 60 transfers the blanking control data to the first buffer 60 in the downstream stage on the basis of the clock signal CLK0” that is the data is output from the first clock because it is output based on the first clock wherein the first clock CLK0 being one of the plurality of the clock signals to various buffers 60); an electrode (fig. 4, 24) configured to receive a voltage based on the first data that is output from the buffer ([0043], note data stored in buffers 60 is stored in second buffer 62 ([0042]), thus voltage based on the first data that is output from the buffer); and
an error detection circuit (28) configured that:
receives the first data and the first error detection code from a clock of a last stage among the plurality of registers ([0032] “The data stored in the first buffer 60 and the second buffers 62 (stored values) are output to the error detection circuit 28” (see discussion above with regards to data output to buffers based on clock signal thus from a clock signal), see annotated figure below to show last stage sending data from buffer to 28);
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generates a second error detection code ([0042] teaches error stored in first buffer 60 is stored in second buffer 62. Paragraph [0041] teaches an error detection symbol such as parity is added to blanking control data. That is, error detection symbol is in data stored in second buffer 62) for detecting an error in the first data from the first data received from the clock of the last stage ([0059] teaches error detection, paragraph [0060] teaches when error is detected retransmission of the blanking data is performed. Paragraph [0062] give the example of an error detected in data D3 (figure 7). Retransmission includes transferring data in order through the first buffer 60 ([0063]-[0064]). In other words, in a case where an error in last stage 62 is detected (last stage 62 below last stage clock signal above), retransmission of the data in order from buffers 60 occurs. Since the data in buffer 62 is from the data of 60 an error in the last stage of 62 is a detection of error in the first data at 60 based on clock signal CL0 (note the claim recites an error detection circuit configured to. Because Hasegawa is configured to detect a second error from the last stage of the clock and correct it via transmission it is configured to detect an error in the first data from the first data received from the last clock stage at 60 (see annotated figure above) that stored in 62)).
Hasegawa et al. teaches the first buffer 60 transfers the blanking control data to the first buffer 60 in the downstream stage on the basis of the clock signal CLK0 ([0029], [0041]), however fails to disclose by what mechanism the clock signal is used as a basis to transmit data to the buffers.
However, Platzgummer et al. teaches “the aperture array contains additional logic circuitry, thus implementing an electronic mask scanning system in which the pattern information is passed by means of shift registers from one aperture to the next within a row” ([0007]). Platzgummer further teaches “single beam blanking is achieved by a continuous data stream and a simplified data line architecture, where only one aperture row (=number of lines.times.one aperture) is to be fed into the PD field per clock cycle, the signal traveling by shift registers over the PD field” ([0013]) and “the blanking signals are derived from feeding lines, each feeding line serving blanking signals for a number of blanking openings, which are propagated through a series of shift registers into a sequence of intermediate buffer means” ([0030]).
Platzgummer modifies Hasegawa by suggesting distributing the clock signals to intermediate buffers by means of shift registers.
Since both inventions are directed towards aperture arrays, it would have been obvious to one of ordinary skill in the art to apply the data to the buffers via series of shift registers as suggested by Platzgummer because it would resolve the problem as to how to transfer the data based on clock signals as suggested by Hasegawa. Moreover, the combination of a shift register with each buffer realizes an efficient provision of the blanking signals to the individual blanking openings ([0030] of Platzgummer).
While Hasegawa teaches error detection via a parity check or calculating a checksum for each shot of via stored values of the first buffer and the second buffer ([0059]), Hasegawa fails to disclose generate a detection signal indicating a match if the first error detection code from the register of the last stage and the second error detection code match and indicating a mismatch if the first error detection code from the register of the last stage and the second error detection code do not match.
However, Verheul et al. teach an error detection circuit (figure) configured to: receive the first data (D3) and the first error detection code (P3) from a register of a last stage (R3) among the plurality of registers (R1-R3);
generate a second error detection code (PG1) for detecting an error in the first data from the first data received from the register of the last stage (PG1 output compared to P3 to determine if error in R3); and
generate a detection signal indicating a match if the first error detection code (P3) from the register of the last stage (R3) and the second error detection code (PG1) match (an out of 0 indicates a match see col. 2, lines 50-53) and indicating a mismatch if the first error detection code from the register of the last stage and the second error detection code do not match (col. 2, lines 56-60).
Verheul modifies the combined device by suggesting a parity comparison of second generated parities to parities input into shift registers.
Since both inventions are directed towards using parities to determine errors, it would have been obvious to one of ordinary skill in the art to apply the circuit of Verheul to the error detection circuit of the combined device because it would resolve how the error is determined by parity checks. Moreover, Verheul allows for less hardware thus reducing cost and simplifies the determination as to whether is an error by a single output (see figure 1 and col. 1, lines 16-21).
Alternatively, Satoh teaches an error detection circuit to generate a detection signal indicating a match if the first error detection code from the register of the last stage and the second error detection code match and the second error detection code match and indicating a mismatch if the first error detection code from the register of the last stage and the second error detection code do not match. Specifically, Satoh teaches
a) checksum data from 86 in figure 5 (first error detection code).
b) Col. 16, lines 37-43 teaches data error has occurred due to non-match and this data is stored in 86 and 801-80n (figures 4-5). This data is fed to the registers 441-44n in figure 5 from 801-80n (i.e. first error detection code). Since register 44n receives data from 801 it includes (first error detection code from the last stage).
c) Last stage register 44n in figure 5 output to checksum 81 (error detection circuit) 81 in figure 5.
d) Both the checksum 86 (i.e. first error detection code) and the second checksum (i.e. from output of 81) are compared at 89. Col. 15, lines 17-22 teaches if it is detected that they do not match, suggests that a single is generated to indicate match or non-match
That is, checksum data (first error detection code) is included in external storage 86 and 801-801n. This data is in communication with last register 44n (i.e. 80n to 41n to register 441). Therefore, checksum 86 includes information from the last stage register. The checksum 86 is compared to checksum output from 81 (second error detection code) and if it is detected that they do not match an alarm is initiated. By detection of mismatch, there is inherently a detection of match.
Satoh modifies the combined device by suggesting a checksum comparison to determine whether an error has occurred instead of an individual parity check as suggested by Hasegawa.
Since both inventions are directed towards error detection using checksum or parity, it would have been obvious to one of ordinary skill in the art to apply the checksum comparison as suggested in Satoh in the combined device because since “the checksum calculating circuit 81 comprises one "1" totaling circuit 82, one adder 83 and two registers 84 and 85 for n bits, e.g., 512 bits, its structure is simpler than that required for a parity check circuit and an ECS circuit, which will require a great number of such circuits and, at the same time, error checking can be performed at a higher speed than in a complex ECS circuit. Consequently, since it is not necessary to lower the speed of data transfer to the BAA 30, an advantage is achieved in that a reduction in throughput of exposure is prevented” (col. 15, lines 23-31). Alternatively, Hasegawa fails to actually teach the checksum detection circuit, therefore applying the comparison of Satoh would resolve the problem as to how to detect errors in the detection circuit of Hasegawa.
Regarding claims 2 and 5, Hasegawa in view of Platzgummer teaches wherein the shift register shifts the first data and the first error detection code at a same time as when second data is sent into the shift register (Hasegawa, retransmission of data being corrected data ([0063]-[0064]) thus first data and first error detection code shifted (i.e. corrected) (see discussion above with respect to blanking control data and modification to include shift registers for distribution of signals by Platzgummer). Paragraph [0064] teaches it is necessary not only to retransmit data in which an error has been detected but also data for subsequent shots. Thus retransmission of shifted or corrected data occurs at the same time as second data), and are input to the error detection circuit input, and the second data is next control data (as indicated in figure 4 all data returns to error detection circuit, wherein the subsequent data is interpreted to be control data as there is no requirement as to what the control data comprises. As discussed above in claim 1, the data is transmitted via a clock signal, however it would be obvious to include a shift register as taught by Platzgummer).
Regarding claims 3 and 6, Hasegawa teaches a control circuit (54) that outputs the first data and the second error detection code to the data output circuit (fig. 1 shows retransmission processing unit 54 controlling deflection control circuit 130, paragraph [0062]-[0064] teaches 54 retrieves error detected in data D3 and retransmits D3. This requires output to the deflection control device as the deflection control device transmits data to the buffers and then to electrodes ([0041] and [0043])).
Claim 4 is commensurate in scope to claim 1 and taught in the citations and discussion above.
Regarding claims 7-121, Hasegawa teaches a charged particle beam writing apparatus comprising: a movable stage (fig. 1, 105); a beam source (201) configured to irradiate the stage with a charged particle beam (as indicated by rays extending from 201 to 105); the blanking aperture array system (204) of claim 1(or 2-6) located between the beam source and the stage (204 between 201 and 105); and a control circuit (54) configured to output the first data and the second error detection code to the data output circuit (see discussion in claim 3 above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL J LOGIE/Primary Examiner, Art Unit 2881
1 Note each of claims 8-12 require identical limitations to claim 7 only different with respect to their dependencies.
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