DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application KR 10-2023-0121490 filed in the Ministry of Intellectual Property (MOIP) on September 13, 2023 and receipt of a certified copy thereof.
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-17) in the reply filed on June 23, 2026 is acknowledged. Claims 18-20 drawn to the non-elected invention have been withdrawn from examination.
Information Disclosure Statement
The information disclosure statement (IDS) filed on April 15, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Objections
Claims 1 and 16 are objected to because of the following informalities:
In claim 1, line 8, “40 at%” should read --40 atomic percent (at%)--. Support can be found at least in paragraph [00154] of the original specification.
In claim 16, line 2, “20 cm2/Vs” should read --20 square centimeter per volt-second (cm2/Vs)-- for clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Hosono et al. US 2020/0287002 in view of Yamazaki et al. US 2012/0175610.
Regarding claim 1, Hosono teaches a display device (e.g., [10]; Fig. 1 and the description thereof; also see Figs. 3-8 that are steps for forming the device in Fig. 1 and the description thereof) comprising:
a substrate (e.g., 110, Fig. 1);
a first transistor (e.g., transistor of 100, Fig. 1) comprising a first active layer (e.g., 130, Fig. 1) disposed on the substrate and a first gate electrode (e.g., 170, Fig. 1) disposed on the first active layer; and
a first gate insulating layer (e.g., 140, Fig. 1) disposed between the first active layer and the first gate electrode.
Hosono does not explicitly teach (i) wherein the first active layer comprises an oxide semiconductor containing indium (In) at a content range of about 40 at% to about 54 at% and (ii) wherein the first gate insulating layer has an emission amount range of oxygen (O2) of about 2.48E+19 Molec./cm3 to about 2.76E+19 Molec./cm3, or an emission amount range of nitrogen monoxide (NO) of about 1.04E+20 Molec./cm3 to about 1.15E+20 Molec./cm3 under heat treatment conditions performed at a temperature range of about 50°C to about 550°C.
Regarding (i), Hosono, however, recognizes that the indium of the oxide semiconductor of the active layer is preferably included, with respect to all cationic species, at a range of 10 atom % to 40 atom %, which is close to the claimed range and/or overlaps the claimed range. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the device of Hosono to include the claimed range since it has been held that where the criticality of the claimed range is not shown and the claimed range is merely close to, overlaps or lies inside ranges disclosed by the prior art, a prima facie case of obviousness exists. MPEP § 2144.05.
Regarding (ii), Yamazaki teaches that in Fig. 3, oxygen molecules in the gate insulating layer 24 are released by heating (e.g., [89]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the gate insulating layer 140 of Hosono may release oxygen molecules by heating as the gate insulating layer 24 of Yamazaki does for reducing oxygen vacancies of the active layer because the materials of the first gate insulating layer 140 of Hosono are the same as those of the gate insulating layer 24 of Yamazaki, for example (e.g., Yamazaki, [92]; Hosono, [130]).
Hosono in view of Yamazaki still does not explicitly teach wherein the first gate insulating layer has an emission amount range of oxygen (O2) of about 2.48E+19 Molec./cm3 to about 2.76E+19 Molec./cm3, or an emission amount range of nitrogen monoxide (NO) of about 1.04E+20 Molec./cm3 to about 1.15E+20 Molec./cm3 under heat treatment conditions performed at a temperature range of about 50°C to about 550°C.
Yamazaki recognizes that in Fig. 3, the gate insulating layer 24 has an emission amount range of oxygen (O2) of preferably 1.0 x1018 molecules/cm.sup.3 or greater (e.g., [89]), which overlaps the claimed range, under heat treatment conditions performed at a temperature range of about 70°C to about 570°C (e.g., [354]), which overlaps the claimed range. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the device of Hosono in view of Yamazaki to include the claimed ranges since it has been held that where the criticality of the claimed ranges is not shown and the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. MPEP § 2144.05.
Regarding claim 2, Hosono in view of Yamazaki teaches the display device of claim 1, wherein the first active layer further contains at least one of gallium (Ga), zinc (Zn), and tin (Sn) (e.g., Hosono, [118]-[122]).
Regarding claim 3, Hosono in view of Yamazaki teaches the display device of claim 2, wherein the first active layer contains indium-gallium-zinc oxide (IGZO), indium-tin-gallium oxide (ITGO), or indium-tin-gallium-zinc oxide (ITGZO) (e.g., Hosono, [118]-[122]).
Regarding claim 4, Hosono in view of Yamazaki teaches the display device of claim 1, wherein the first gate insulating layer contains silicon oxide (e.g., Hosono, [130]).
Regarding claim 5, Hosono in view of Yamazaki teaches the display device of claim 1 as discussed above.
Hosono further teaches the semiconductor device 100 is any one of a TFT (thin-film transistor), a photovoltaic cell, and an OLED (organic light emitting diode) (e.g., [21]). Yamazaki further teaches the display device further comprising a pixel (e.g., 902, Fig. 8), wherein the pixel comprises a pixel circuit comprising the first transistor and a light emitting element connected to the pixel circuit (e.g., Fig. 8, [274]-[293], [275]; Fig. 4B). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hosono in view of Yamazaki to include the display device further comprising a pixel, wherein the pixel comprises a pixel circuit comprising the first transistor and a light emitting element connected to the pixel circuit because such a modification for its conventional use would have been a common sense choice by one skilled in the semiconductor art. MPEP §2143.
Regarding claim 6, Hosono in view of Yamazaki teaches the display device of claim 5 as discussed above.
Yamazaki further recognizes that the pixel 902 includes a plurality of transistors and the transistor of one embodiment of the present invention can be used (e.g., Fig. 8, [215], [225]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the device of Hosono in view of Yamazaki to include wherein the pixel further comprises: a second transistor comprising a second active layer disposed on the substrate and a second gate electrode disposed on the second active layer; and a second gate insulating layer disposed between the second active layer and the second gate electrode because such a modification for its conventional use would have been a common sense choice by one skilled in the semiconductor art. MPEP §2143.
Regarding claim 7, Hosono in view of Yamazaki teaches the display device of claim 6, wherein the second active layer is disposed in a same layer as the first active layer, wherein the second active layer contains a same oxide semiconductor as the first active layer (see the discussion regarding claim 6 above).
Regarding claim 8, Hosono in view of Yamazaki teaches the display device of claim 6, wherein the second gate insulating layer is disposed in a same layer as the first gate insulating layer, wherein the second gate insulating layer contains a same insulating material as the first gate insulating layer (see the discussion regarding claim 6 above).
Regarding claim 9, Hosono in view of Yamazaki teaches the display device of claim 5, further comprising a driver (e.g., Yamazaki, 904, Fig. 8, [210]) disposed on the substrate and electrically connected to the pixel.
Regarding claim 10, Hosono in view of Yamazaki teaches the display device of claim 9, wherein the driver comprises: a third transistor comprising a third active layer disposed on the substrate and containing a same oxide semiconductor as the first active layer, wherein a third gate electrode is disposed on the third active layer; and a third gate insulating layer disposed between the third active layer and the third gate electrode and containing a same insulating material as the first gate insulating layer (e.g., Yamazaki, 911 in 904, Fig. 8).
Regarding claim 11, Hosono in view of Yamazaki teaches the display device of claim 1, wherein the first active layer comprises a first channel region (e.g., Hosono, first channel region of 130 overlapping 170, Fig. 1) overlapping the first gate electrode, and a first drain region (e.g., Hosono, first drain region of 130 overlapping 162, Fig. 1) and a first source region (e.g., Hosono, first source region of 130 overlapping 160, Fig. 1) located on both sides of the first channel region, wherein the first gate insulating layer is an insulating pattern disposed only on a portion of the first active layer comprising the first channel region and exposing the first drain region and the first source region (e.g., Hosono, Fig. 1).
Regarding claim 12, Hosono in view of Yamazaki teaches the display device of claim 1, further comprising an interlayer insulating layer (e.g., Hosono, 150, Fig. 1) disposed on the substrate and covering the first active layer and the first gate electrode, wherein the first transistor further comprises at least one of a first drain electrode (e.g., Hosono, 162, Fig. 1) disposed on the interlayer insulating layer and connected to a part of the first active layer, and a first source electrode (e.g., Hosono, 160, Fig. 1) disposed on the interlayer insulating layer and connected to another part of the first active layer.
Regarding claim 13, Hosono in view of Yamazaki teaches the display device of claim 12, further comprising a first passivation layer (e.g., Hosono, 180, Fig. 1) disposed on the interlayer insulating layer and covering the first transistor.
Regarding claim 14, Hosono in view of Yamazaki teaches the display device of claim 13, wherein the first passivation layer comprises an inorganic insulating layer containing silicon nitride (e.g., Hosono, [182]).
Regarding claim 15, Hosono in view of Yamazaki teaches the display device of claim 13, wherein the first passivation layer comprises an inorganic insulating layer containing silicon oxide (e.g., Hosono, [182]).
Yamazaki further teaches a second passivation layer (e.g., 942, Fig. 8) disposed on the first passivation layer, and wherein the second passivation layer comprises an inorganic insulating layer containing silicon nitride (e.g., [230]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hosono in view of Yamazaki to include a second passivation layer disposed on the first passivation layer, and wherein the second passivation layer comprises an inorganic insulating layer containing silicon nitride because such a modification for its conventional use would have been a common sense choice by one skilled in the semiconductor art. MPEP §2143.
Regarding claim 16, Hosono in view of Yamazaki teaches the display device of claim 1 ad discussed above.
Hosono and Yamazaki further recognize that the active layer of the transistor includes In-Ga-Zn based oxide (e.g., Hosono, [118]-[122]; Yamazaki, [116]). It has been well known in the art that a transistor including In-Ga-Zn based oxide used in display devices typically targets an electron mobility in a range of 10 cm2/Vs to about 50 cm2/Vs, which overlaps the claimed range. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the device of Hosono in view of Yamazaki may have an electron mobility in the claimed range for example.
Regarding claim 17, Hosono in view of Yamazaki teaches the display device of claim 1 ad discussed above.
Hosono and Yamazaki further recognize that the active layer of the transistor includes In-Ga-Zn based oxide (e.g., Hosono, [118]-[122]; Yamazaki, [116]). It has been well known in the art that a transistor including In-Ga-Zn based oxide used in display devices typically targets a threshold voltage in a range of about -0.5 V to about +2.0 V, which overlaps the claimed range. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the device of Hosono in view of Yamazaki may have a threshold voltage in the claimed range for example.
Conclusion
The art made of record and not applied to the rejection is considered pertinent to applicant's disclosure. It is cited primarily to show inventions relevant to the examination of the instant invention. For example, Yamazaki US 2012/0175610 relates to a display device including a transistor with a gate insulating layer that emits/releases oxygen under heat treatment conditions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 September 4, 2026
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