DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim that this application is a divisional application of U.S. Application Serial No. 17/833,356, filed June 6, 2022, which is a continuation application of U.S. Patent Application Serial No. 17/201,147, filed March 15, 2021, which is a continuation application of U.S. Patent Application Serial No. 16/529,357, filed August 1, 2019, which claims priority to U.S. Provisional Patent Application Serial No. 62/753,295, entitled “Merged Source/Drain Features” and filed on October 31, 2018.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/15/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1, 8, and 15 are objected to because of the following informalities:
Regarding claim 1, “comprise” on line 8 should be changed to “comprises”.
Regarding claim 8, “comprise” on line 6 should be changed to “comprises”.
Regarding claim 15, “silico nitride” on line 2 should be changed to “silicon nitride”.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. US 10,950,730 B2 (will be referred as Lin) in view of Kwok (US 2011/0073952 A1).
Instant Application- 18/635,834
US Pat. No. US 10,950,730 B2 (Lei)
Claim 8:
A method, comprising:
recessing a fin extending from a substrate;
forming a base epitaxial feature on the recessed fin;
forming a bar-like epitaxial feature on the base epitaxial feature; and
forming a conformal epitaxial feature on the bar-like epitaxial feature,
wherein the forming of the base epitaxial feature comprises use of only one of silane (SiH4) and dichlorosilane (SiCl2H2),
wherein the forming of the bar-like epitaxial feature comprises use of both silane (SiH4) and dichlorosilane (SiCl2H2).
Claim 1:
A method comprising:
recessing a fin extending from a substrate;
forming a base epitaxial feature on the recessed fin;
forming a bar-like epitaxial feature on the base epitaxial feature; and
forming a conformal epitaxial feature on the bar-like epitaxial feature,
wherein the forming of the bar-like epitaxial feature comprises in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration,
wherein the forming of the conformal epitaxial feature comprises in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
Claim 5:
The method of claim 1,
wherein the forming of the bar-like epitaxial feature comprises: using a plurality of silicon precursors comprising silane (SiH4) and dichlorosilane (SiCl2H2).
Regarding claim 8, Lin claims 1 and 5 recites the limitations of claim 8, as indicated in bold in the table above.
Lin, however, does not teach that the forming of the base epitaxial feature comprises use of only one of silane (SiH4) and dichlorosilane (SiCl2H2).
Kwok, on the other hand, teaches a method (Figs. 1-7, [0009]), wherein the forming of the base epitaxial feature (SiGe region 36, Fig. 3, [0017]: “SiGe region 36, which may also be referred to as a source/drain stressor 36, is epitaxially grown in recesses 34 by selective epitaxial growth (SEG).”) comprises use of only one of silane (SiH4) ([0017]: “the precursors may include Si-containing gases and Ge-containing gases, such as SiH4 and GeH4, respectively”, therefore only SiH4 -among SiH4 and SiCl2H2 is used to form the first epitaxial layer) and dichlorosilane (SiCl2H2).
A person of ordinary skill in the art before the effective filing date of the claimed invention would already know that epitaxial deposition of silicon or silicon germanium layers using silane provides faster deposition rates and low deposition temperatures, as evidenced by Hartmann (Introduction; Hartmenn et al., A benchmarking of silane, disilane and dichlorosilane for the low temperature growth of group IV layers, Thin Solid Films, Volume 520, Issue 8, 2012, Pages 3185-3189, ISSN 0040-6090, https://doi.org/10.1016/j.tsf.2011.10.164.). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the base epitaxial feature using only silane (SiH4), out of silane and dichlorosilane (SiCl2H2), to obtain faster deposition rates and lower deposition temperatures.
Claims 9-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5 of Lin in view of Kwok (US 2011/0073952 A1) as applied to claim 8 above, and further in view of claims 2-4 of Lin.
Instant Application- 18/635,834
US Pat. No. US 10,950,730 B2 (Lei)
Claim 9:
The method of claim 8,
wherein the forming of the bar-like epitaxial feature comprises in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration,
wherein the forming of the conformal epitaxial feature comprises in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
Claim 10:
The method of claim 9, where the forming of the base epitaxial feature comprises in-situ doping the base epitaxial feature with the n-type dopant at a third doping concentration equal to or lower than the first doping concentration.
Claim 11:
the method of claim 9, wherein the first doping concentration is between about 3 x 1021 atoms per cm3 and about 4 x 1021 atoms per cm3.
Claim 12:
The method of claim 9, wherein the second doping concentration is between about 4 x 1021 atoms per cm3 and about 5 x 1021 atoms per cm3.
Claim 1:
A method comprising:
recessing a fin extending from a substrate;
forming a base epitaxial feature on the recessed fin;
forming a bar-like epitaxial feature on the base epitaxial feature; and
forming a conformal epitaxial feature on the bar-like epitaxial feature,
wherein the forming of the bar-like epitaxial feature comprises in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration,
wherein the forming of the conformal epitaxial feature comprises in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
Claim 2:
The method of claim 1, where the forming of the base epitaxial feature comprises in-situ doping the base epitaxial feature with the n-type dopant at a third doping concentration equal to or lower than the first doping concentration.
Claim 3:
the method of claim 1, wherein the first doping concentration is between about 3 x 1021 atoms per cm3 and about 4 x 1021 atoms per cm3.
Claim 4:
The method of claim 1, wherein the second doping concentration is between about 4 x 1021 atoms per cm3 and about 5 x 1021 atoms per cm3.
Regarding claim 9-12, Lin claims 1-5 contains all the limitations of claims 9-12, as indicated in bold in the tables above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kwok (US 2013/0089959 A1) in view of Kim (US 2017/0148797 A1).
Regarding claim 1, Kwok teaches a method (Figs. 1-7, [0009]), comprising:
etching a substrate (substrate 20, Fig. 1, [0013]; while Kwon is silent on the method of forming the fin on the substrate, a person of ordinary skill in the art would already know that etching is a common method in the semiconductor manufacturing to form fins (see as evidence Lee (US 2017/0256456 A1), Figs. 1-2, [0015]), and application of a known method to obtain a predictable result does not provide an inventive concept (see MPEP 2143)) to form a fin (fin 24, Fig. 1, [0013]), the substrate (substrate 20, Fig. 1) having a top facing surface comprising a (100) plane ([0014]: “substrate 20 has a surface orientation of (100)”);
recessing the fin (recess 34 formed on the fin 24, Figs. 2A and 3, [0015]) to form a recess (recess 34, Figs. 2A and 3);
depositing a first epitaxial layer (SiGe region 36, Fig. 3, [0017]: “SiGe region 36, which may also be referred to as a source/drain stressor 36, is epitaxially grown in recesses 34 by selective epitaxial growth (SEG).”) over the recess (recess, 34, Fig. 3);
depositing a second epitaxial layer (Si interlayer 60, Fig. 5, [0022], while Kwon is silent on that the Si interlayer is epitaxially deposited, a person of ordinary sill in the art before the effective filing date of the claimed invention would already know that depositing a layer epitaxially in semiconductor devices improves the quality of the layer and the electrical characteristics as evidenced by Bourget et al. (MKS Instruments Handbook, 2nd Edition, 2017, pages 35-41, https://www.mks.com/n/silicon-epitaxial-thin-films). Therefore, application of a known common technique to a known device to obtain a predictable result of improved layer quality does not provide an inventive concept (see MPEP 2143(I)(E))) over the first epitaxial layer (SiGe region 36, Fig. 5); and
depositing a third epitaxial layer (SiGe region 48, Fig. 6, [0020]: “process conditions for the epitaxial process are changed to form SiGe region 48 on SiGe region 36”) over the second epitaxial layer (Si interlayer 60, Fig. 5),
wherein the depositing of the first epitaxial layer (SiGe region 36, Fig. 3) comprise use of only one of silane (SiH4) ([0017]: “the precursors may include Si-containing gases and Ge-containing gases, such as SiH4 and GeH4, respectively”, therefore only SiH4 -among SiH4 and SiCl2H2 is used to form the first epitaxial layer) and dichlorosilane (SiCl2H2).
Kwok, on the other hand, is silent on the gas composition during deposition of the second epitaxial layer, and therefore does not teach that
the depositing of the second epitaxial layer comprises use of both silane (SiH4) and dichlorosilane (SiCl2H2).
Kim, on the other hand, teaches a method for manufacturing a semiconductor device (Figs. 1-59, [0095]), wherein the source/drain region (source/drain layer structure 222, Fig. 22, [0152]) comprises epitaxially deposited semiconductor layers (first semiconductor layer 202a ([0128]), second semiconductor layer 202b ([0128]), third semiconductor layer 202c ([0142]) and first capping layer 212 ([0149]), Fig. 22), wherein the first capping layer 212 is analogous to the second epitaxial layer of Kwok in terms of its shape and its conformal coverage of the surfaces of underlying semiconductor layers. Kim further discloses that, to facilitate coverage of the upper surface of the third semiconductor layer 202c and of the lower side surface of the second semiconductor layer 202b (Fig. 22), both silane (SiH4) and dichlorosilane (SiCl2H2) should be used during deposition.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the capping layer 212 of Kim is analogous to the second epitaxial layer of Kwok in terms of its conformal coverage of the surfaces of underlying layers, and therefore a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the second epitaxial layer in the method of Kwok according to the teachings of Kim by depositing the second epitaxial layer using both silane (SiH4) and dichlorosilane (SiCl2H2), which facilitates the coverage of both the upper and lower surfaces of underlying layers.
Regarding claim 2, while Kwok in view of Kim teaches the method of claim 1,
neither Kwok nor Kim explicitly discloses that depositing of the second epitaxial layer deposits faster on the (100) plane than on other crystal planes of the substrate.
Kwok, however, teaches that the growth rate on surfaces having (111) surface orientations is lower than that of other planes such as (110) and (100) planes ([0019]). Considering (1) that the second epitaxial layer of Kwon in view of Kim (Si interlayer 60, Fig. 5) is silicon, which is also the case in the current application, (2) that the substrate is doped silicon (Kwon, [0013]), (3) that the orientation of layers is similar (see claim 1 rejection) in Kwon in view of Kim and in the current application, and (4) that the deposition gases are similar, the deposition rate will be intrinsically faster on the (100) plane than on other crystal planes of the substrate (see MPEP 2112.01).
Regarding claim 3, Kwok in view of Kim teaches the method of claim 1, wherein
Kwok further teaches that the substrate (substrate 20, Fig. 5, [0013]) comprises silicon ([0013]: “silicon“).
Regarding claim 4, while Kwok in view of Kim teaches the method of claim 1,
Kwok is silent on that if the second and third epitaxial layers are doped or not, and therefore does not teach that
the forming of the second epitaxial layer comprises in-situ doping the second epitaxial layer with an n-type dopant at a first doping concentration,
the forming of the third epitaxial layer comprises in-situ doping the third epitaxial layer with the n-type dopant of a second doping concentration greater than the first doping concentration.
Kim, on the other hand, teaches a method for manufacturing a semiconductor device (Figs. 1-59, [0095]), wherein the forming of the epitaxial semiconductor layers of the source/drain region (source/drain layer structure 222, Fig. 22, [0152]) comprises first to third selective epitaxial growth (SEG) processes to deposit the first semiconductor layer 202a (Fig. 22, [0130]) via first SEG process ([0130]), second semiconductor layer 202b (Fig. 22, [0131]) via second SEG process ([0131]), and third semiconductor layer 202c (Fig. 22, [0142]) via third SEG process ([0142]). Kim further discloses that the first to third SEG processes may include n-type impurity source gas for forming n-doped semiconductor layers ([0164]), and the impurity concentration of the third semiconductor layer 202c (Fig. 22, [0144]) greater than the impurity concentration of the second semiconductor layer 202b (Fig. 22, [0144]: while the impurities in the provided embodiment in Kim is p-type, a person of ordinary skill in the art would understand that same principles applies to n-type impurities in an n-type device). Thus, Kim teaches that
the forming of the second epitaxial layer (second semiconductor layer 202b, Fig. 22) comprises in-situ doping ([0164]: n-type impurity source gas is provided during deposition process, which leads to in-situ doping) the second epitaxial layer (second semiconductor layer 202b, Fig. 22) with an n-type dopant ([0164]) at a first doping concentration ([0144]: Kim does not provide the amount of doping),
the forming of the third epitaxial layer (third semiconductor layer 202c, Fig. 22) comprises in-situ doping (([0164]: n-type impurity source gas is provided during deposition process, which leads to in-situ doping) the third epitaxial layer (third semiconductor layer 202c, Fig. 22) with the n-type dopant ([0164]) of a second doping concentration ()greater than the first doping concentration ([0144]: “the third and sixth semiconductor layers 202c and 204c may be formed to have a p-type impurity concentration greater than that of the second and fifth semiconductor layers 202b and 204b by controlling flow rates of the p-type impurity source gas.”).
Kim further discloses that the impurity doping concentration becomes increasingly higher in upper layers in the epitaxial layers of the source/drain region ([0010]), which contributes to the inventive concept of providing a semiconductor device having good characteristics and method of manufacturing semiconductor devices having good characteristics ([0006]-[0010]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to dope the epitaxial layers in the method of Kwok in view of Kim according to the teachings of Kim such that
the forming of the second epitaxial layer comprises in-situ doping the second epitaxial layer with an n-type dopant at a first doping concentration,
the forming of the third epitaxial layer comprises in-situ doping the third epitaxial layer with the n-type dopant of a second doping concentration greater than the first doping concentration,
which provides the benefit of obtaining a method of manufacturing a semiconductor device having good characteristics ([0006]-[0010]).
Regarding claim 5, while Kwok in view of Kim teaches the method of claim 4,
Kwok and Kim do not teach that the first doping concentration is between about 3 x 1021 atoms per cm3 and about 4 x 1021 atoms per cm3.
However, the combination of Kwok and Kim teaches that the first doping concentration is higher than the doping concentration of the first epitaxial layer (see claim 4 rejection above) and the doping concentration of first epitaxial layer (Kwok: SiGe region 36, Fig. 3) is “between about 1x1019/cm3 and about 1x1021/cm3” (Kwok, [0018]). Therefore, the combination of Kwok and Kim teaches that the first doping concentration is above about 1x1019/cm3 and about 1x1021/cm3. Therefore, the range of first doping concentration provided by the prior art overlaps with the range of first doping provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the first doping concentration can be optimized by routine experimentation to achieve desired electrical characteristics of the manufactured device (see MPEP 2144.05(II)). Therefore, the range of values provided does not hold an inventive subject matter.
Regarding claim 6, while Kwok in view of Kim teaches the method of claim 4,
Kwok and Kim do not teach that the second doping concentration is between about 4 x 1021 atoms per cm3 and about 5 x 1021 atoms per cm3.
However, the combination of Kwok and Kim teaches that the second doping concentration is higher than the doping concentration of the first epitaxial layer (see claim 4 rejection above) and the doping concentration of first epitaxial layer (Kwok: SiGe region 36, Fig. 3) is “between about 1x1019/cm3 and about 1x1021/cm3” (Kwok, [0018]). Therefore, the combination of Kwok and Kim teaches that the second doping concentration is above about 1x1019/cm3 and about 1x1021/cm3. Therefore, the range of second doping concentration provided by the prior art overlaps with the range of second doping provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the second doping concentration can be optimized by routine experimentation to achieve desired electrical characteristics of the manufactured device (see MPEP 2144.05(II)). Therefore, the range of values provided does not hold an inventive subject matter.
Regarding claim 7, Kwok in view of Kim teaches the method of claim 4, where
the combination of Kwok and Kim further teaches that the forming of the first epitaxial layer (Kwok: SiGe region 36, Fig. 3, [0018]) comprises in-situ doping (Kwok, [0018]: “During the epitaxial process for forming SiGe region 36, p-type impurities such as boron may be doped with the proceeding of the epitaxy. … In alternative embodiments, no p-type and n-type impurities are doped”) the first epitaxial layer (Kwok: SiGe region 36, Fig. 3) with the n-type dopant (Kwok, [0018]: the embodiment with n-type doping is considered here) at a third doping concentration (Kwok, [0018]: “between about 1x1019/cm3 and about 1x1021/cm3) equal to or smaller (see claim 4 rejection above describing the method of Kwon in view of Kim (as applied to claim 1) further modified by Kim ) than the first doping concentration.
Claims 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148797 A1) in view of Huang (US 2010/0317177 A1).
Regarding claim 8, Kim teaches a method (Figs. 1-59, [0105]), comprising:
recessing a fin (fist active fin 102, Figs.10 and 13, [0123]-[00125]) extending from a substrate (substrate 100, Fig. 13, [0107]);
forming a base epitaxial feature (first semiconductor layer, 202a, Fig. 18, [0128]-[0129]: formed by first selective epitaxial growth (SEG) process) on the recessed fin (fist active fin 102, Fig. 18);
forming a bar-like epitaxial feature (comprising second semiconductor layer 202b ([0128]-[0129]: formed by second SEG process) and third semiconductor layer 202c ([0142]: formed by third SEG process; [0151]: “The first to third semiconductor layers 202a, 202b and 202c sequentially stacked on the first active fin 102 and the first capping layer 212 on the second and third semiconductor layers 202b and 202c may form a first source/drain layer structure 222.”; see top view Fig. 21 showing the source/drain layer structure 222 having a bar-like shape, Fig. 22) on the base epitaxial feature (first semiconductor layer, 202a, Fig. 22); and
forming a conformal epitaxial feature (first capping layer 212, Fig. 22, [0149]: formed by a fourth SEG process) on the bar-like epitaxial feature (comprising second semiconductor layer 202b and third semiconductor layer 202c, Fig. 22),
wherein the forming of the bar-like epitaxial feature (comprising second semiconductor layer 202b and third semiconductor layer 202c, Fig. 22) comprises use of both silane (SiH4) and dichlorosilane (SiCl2H2) ([0129]: “The first SEG process may be performed using e.g., silane (SiH4) gas, disilane (Si2H6) gas, dichlorosilane (DCS) (SiH2Cl2) gas, etc.).” and [0131]:” the second SEG process may be performed using substantially the same gases as the first SEG process”.)
Kim, however, does not teach that
the forming of the base epitaxial feature comprise use of only one of silane (SiH4) and dichlorosilane (SiCl2H2).
Huang, on the other hand, teaches methods of depositing silicon germanium epitaxial layers on silicon substrates (substrate 200, Fig. 1, [0013]-[0014]). Huang discloses that “SiGe layers grown with dichlorosilane typically result in layers having a smooth surface, but with undesirably slow deposition rates. Thus, dichlorosilane precursors undesirably limit process throughput. Alternatively, SiGe layers may be grown using silane precursors, which tend to increase the deposition rate. However, such deposited layers typically have an undesirably rough surface. SiGe layers having rough surfaces may result in poor electrical contact with adjacent layers coupled thereto. In addition, the rough surface can result in device breakdown, or poor power consumption in devices utilizing such SiGe layers” ([0003]). Huang further teaches that depositing first layer on to a semiconductor substrate with dichlorosilane cover defects in the surface of the substrate and provide a smooth surface from which to grow a bulk SiGe layer ([0015]-[0017]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the base epitaxial feature is the first epitaxial layer directly on the fin structure (first active fin 102, Fig. 22) which is the continuation of the substrate (substrate 100, Fig. 22), and therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Kim to deposit the base epitaxial feature using dichlorosilane (SiCl2H2), but not silane, to cover defects in the surface of the fin structure, as taught by Huang, which provides the benefit of obtaining a smooth surface from which the next SiGe epitaxial layers can be grown, and consequently improving the quality of the device structure.
Regarding claim 13, Kim in view of Huang teaches the method of claim 8,
wherein Kim further teaches that the method comprises:
before the recessing (see Figs. 8 and 10-11 showing the step of the method before recessing), forming a gate spacer (first gate spacers 162, Figs. 10-11, [0121]) along sidewalls (see the top view as shown in Fig. 12 where the gate spacers 162 run along the small portions of the sidewalls of the fins) of the fin (fist upper active fin 102a, Figs.11-12),
wherein the recessing is performed such that a top surface of the fin (top surface of the fist upper active fin 102a) is lower than a top surface of the gate spacer (top surface of first gate spacers 162, Figs. 13-14: the top surface of the gate spacers is above the top surface of the recessed fins).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148797 A1) in view of Huang (US 2010/0317177 A1) as applied to claims 8 and 13 above, and further in view of Park (US 2017/0317213 A1).
Regarding claim 14, while Kim in view of Huang teaches the method of claim 13,
neither Kim nor Huang teaches that the gate spacer comprises a two-film configuration or a three-film configuration.
Park, on the other hand, teaches a method for fabricating a FinFET device (Figs. 1-36, [0010]), wherein the gate spacer (gate spacer structure 212, Fig. 36, [0033]) comprises a two-film configuration (a silicon oxycarbonitride (SiOCN) pattern (first spacer 182, [0005]) and a silicon dioxide (SiO2) pattern (offset pattern 202, [0041]), Fig. 36, claim 1) or a three-film configuration.
Park further teaches that the gate spacer structure which includes the offset pattern having a dielectric constant lower than that of silicon nitride or silicon oxycarbonitride, and having a band gap higher than that of silicon nitride or silicon oxycarbonitride reduces the leakage current through the gate spacer structure and decreases the parasitic capacitance between the gate structures, thereby leading to a semiconductor device with good electrical characteristics ([0008]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Kim in view of Huang according to the teachings of Park to form the gate spacer in a two-film configuration to improve the electrical characteristics of the device manufactured by the method.
Regarding claim 15, Kim in views of Huang and Park teaches the method of claim 14, wherein
the combination of Kim, Huang, and Park further teaches that
the two-film configuration (a silicon oxycarbonitride (SiOCN) pattern (first spacer 182, [0005]) and a silicon dioxide (SiO2) pattern (offset pattern 202, [0041]), see claim 14 rejection above) comprises a silicon oxide film ([0041]: offset pattern 202 is silicon dioxide) and a silico nitride film ([0005]: first spacer 182 is silicon oxycarbonitride, which is considered a carbon and oxygen containing silicon nitride film),
wherein the three-film configuration comprises two silicon oxide films and one silicon nitride film sandwiched between the two silicon oxide films.
Allowable Subject Matter
Claims 9-12 are rejected on the basis of double patenting, and each is also dependent upon a rejected base claim. These claims would be allowable if the double rejections on these claims and the base claim are overcome, and if these claims are rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, disclosing the limitation that “the conformal epitaxial feature comprises in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration”, this claim would be allowable if the double patenting rejections on claims 8-9 are overcome, and if the limitation above is incorporated in a claim combining claims 8 and 9.
Regarding the closest prior art, Kim (US 2017/0148797 A1) in view of Huang (US 2010/0317177 A1) teaches all the limitations of claim 8 (see claim 8 rejection above), and Kim further teaches that
the forming of the bar-like epitaxial feature (comprising second semiconductor layer 202b and third semiconductor layer 202c, Fig. 22) comprises in-situ doping the bar-like epitaxial feature with an n-type dopant ([0164]: first to third SEG processes may include n-type impurity source gas for forming n-doped semiconductor layers) at a first doping concentration (p-type impurity concentration, [0144]: while Kim teaches the doping concentrations considering layers with p-type doping, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the same principles applies to the case of n-type impurities in n-type epitaxial layers).
Kim and Huang, however, fail to teach that the forming of the conformal epitaxial feature (first capping layer 212, Fig. 22) comprises in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
Because the conformal epitaxial feature of Kim in view of Huang is actually a capping layer for the purpose of protecting the underlying epitaxial layers during post processing (Kim, [0150]: “The first and second capping layers 212 and 214 may protect the first to third semiconductor layers 202a, 202b and 202c, and the fourth to sixth semiconductor layers 204a, 204b and 204c, respectively, from a heat treatment subsequently performed”), there is no obvious motivation or advantage to dope this layer at any specific doping concentration. Therefore, claim 9 includes allowable subject matter, but is rejected due to reasons mentioned above.
Claims 10-12, which are dependent on claim 9, are also rejected, but would be otherwise allowable if the double patenting rejections and the rejection on claim 9 are overcome.
Claim 16-20 are allowed.
Claim 16 is allowed, because the references of the Prior Art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitation that “the conformal epitaxial layer comprises in-situ doping the conformal epitaxial layer with a second doping concentration greater than the first doping concentration” as recited in claim 16, in combination with the remaining structural and methodological components of claim 16.
Regarding the relevant prior art, Kim (US 2017/0148797 A1) is identified as the closest prior art. Accordingly, Kim teaches a method (Figs. 1-59, [0105]), comprising:
receiving a workpiece (the structure shown in Fig. 10, [0121]) comprising:
a substrate (substrate 100, Fig. 10, [0119]),
an isolation feature (isolation pattern 120, Fig. 10, [0114]) disposed on the substrate (substrate 100, Fig. 10),
a fin (first active Fin 102, Fig. 10, [0117]) extending from the substrate (substrate 100, Fig. 10) and rising above the isolation feature (isolation pattern 120, Fig. 10),
a spacer (first fin spacer 172, Fig. 10 (see also the top view in Fig. 9), [0121]) disposed along sidewalls of the fin (first active Fin 102, Figs. 9-10); and
recessing ([0123]-[00125]) the fin (first active Fin 102, Figs. 10 and 13) until a top surface of the fin (top surface of first upper active pattern 102a, Fig. 13, [0114]) is lower than a top surface of the spacer (top surface of the first fin spacer 172, Fig. 10, [0124]: spacers are removed after recessing the fins and therefore, the top surface of the fins are recessed below the top surface of the spacers);
forming a base epitaxial feature (first semiconductor layer, 202a, Fig. 18, [0128]-[0129]: formed by first selective epitaxial growth (SEG) process) on the recessed fin (fist active fin 102, Fig. 18);
forming a bar-like epitaxial feature (comprising second semiconductor layer 202b ([0128]-[0129]: formed by second SEG process) and third semiconductor layer 202c ([0142]: formed by third SEG process; [0151]: “The first to third semiconductor layers 202a, 202b and 202c sequentially stacked on the first active fin 102 and the first capping layer 212 on the second and third semiconductor layers 202b and 202c may form a first source/drain layer structure 222.”; see top view Fig. 21 showing the source/drain layer structure 222 having a bar-like shape, Fig. 22) on the base epitaxial feature (first semiconductor layer, 202a, Fig. 22); and
forming a conformal epitaxial layer (first capping layer 212, Fig. 22, [0149]: formed by a fourth SEG process) on the bar-like epitaxial feature (comprising second semiconductor layer 202b and third semiconductor layer 202c, Fig. 22),
wherein the forming of the bar-like epitaxial feature (comprising second semiconductor layer 202b and third semiconductor layer 202c, Fig. 22) comprises in-situ doping ([0012] and [0073]: n-type impurity source gases are provided during the deposition processes, which leads to in-situ doping) the bar-like epitaxial feature (comprising second semiconductor layer 202b and third semiconductor layer 202c, Fig. 22) with an n-type dopant ([0012]) at a first doping concentration ([0012]: Kim does not quantify the doping concentrations of individual layers, but provides comparative information about doping concentrations between layers).
Kim, however, fails to teach that
the forming of the conformal epitaxial layer comprises in-situ doping the conformal epitaxial layer with a second doping concentration greater than the first doping concentration.
Because the conformal epitaxial feature of Kim is actually a capping layer for the purpose of protecting the underlying epitaxial layers during post processing ([0150]: “The first and second capping layers 212 and 214 may protect the first to third semiconductor layers 202a, 202b and 202c, and the fourth to sixth semiconductor layers 204a, 204b and 204c, respectively, from a heat treatment subsequently performed”), there is no obvious motivation or advantage to dope this layer at any specific doping concentration. Therefore, claim 16 is allowed.
Claims 17-20 are also allowed, because these claims inherit the allowable subject matter from claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang (US 2015/0303118 A1) teaches a method of manufacturing a FinFET device comprising a source/drain region with three epitaxial layers, which is relevant to all claims.
Jung (US 2019/0296144 A1) teaches a method of manufacturing a FinFET device comprising a source/drain region with three epitaxial layers, which is relevant to all claims.
Greene (US 2019/0006506 A1) teaches a method of manufacturing a FinFET with multi-layer gate spacers, which is relevant to claims 14-15.
Ko (US 2017/0154991 A1) teaches a method of manufacturing a FinFET with multi-layer gate spacers, which is relevant to claims 14-15.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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