DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on February 3, 2026.
Claims 1-20 are pending. Claims 1, 5, 10, 12-13, 17 and 19 are amended. Claims 1, 10 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on February 3, 2026. These drawings are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 5-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al. (US 5835400).
Regarding independent claim 1, Jeon et al. disclose a method [Fig. 3], comprising:
charging a bit line to a read voltage level [see Fig. 2, the first bit line BL1 then transitions from a precharged level to one of two levels 88 or 66, col. 2, lines 30-32];
coupling the bit line [Fig. 4: BL1] to a memory element [Fig. 4: CO];
adjusting a voltage level of the bit line from the read voltage level according to a data bit stored in the memory element [see Fig. 2, depending on the value of the data (i.e., logic 1 or logic 0) stored in the ferroelectric capacitor 104, the first bit line BL1 then transitions from a precharged level to one of two levels 88 or 66, col. 2, lines 29-32];
calculating a signal differentiation according to a first polarization difference [Fig. 3: dQ1] and a second polarization difference [Fig. 3: dQ0] of the memory element [col. 4, lines 51-58], wherein the first polarization difference and the second polarization difference correspond to a first logic value and a second logic value, respectively [col. 4, lines 47-58];
and increasing the read voltage level when the signal differentiation is decreased [Jeon et al. teach measurement of the magnitude of dQ1 versus dQ0 can be performed by monitoring the induced potential on the bit line upon application of the read pulse (col. 4, lines 51-54). Moreover, Jeon et al.’s Fig. 3 teaches the measurable bit line signal differentiation is a function of the sub-coercive read pulse magnitude (col. 4, lines 47-49). Therefore, under MPEP 2112, the claimed increasing of read voltage when signal differentiation decreases is an inherent result of operating the disclosed nondestructive ferroelectric read system to obtain the disclosed measurable dQ1/dQ0 read distinction],
wherein the read voltage level [Fig. 3: -Va] is smaller than a coercive voltage level [Fig. 3: -Vc] of the memory element [col. 4, lines 26-29].
Regarding claim 2, Jeon et al. disclose when a voltage difference between two terminals of the memory element is approximately equal to the coercive voltage level, a polarization of the memory element is approximately equal to zero [see Fig. 3].
Regarding claim 5, Jeon et al. disclose further comprising:
determining the read voltage level according to the signal differentiation [col. 4, lines 33-46],
wherein the first logic value and the second logic value are different from each other [col. 4, lines 47-58].
Regarding claim 6, Jeon et al. disclose wherein
the first polarization difference [Fig. 3: dQ0] is a difference between a first polarization [Fig. 4: point B] and a second polarization [Fig. 4: point E],
the second polarization difference [Fig. 3: dQ1] is a difference between a third polarization [Fig. 3: point A] and a fourth polarization [Fig. 3: point C],
each of the first polarization [Fig. 4: point B] and the third polarization [Fig. 4: point A] corresponds to a zero voltage level [see Fig. 4], and
each of the second polarization [Fig. 4: point C] and the fourth polarization [Fig. 4: point E] corresponds to the read voltage level [see Fig. 4].
Regarding claim 7, Jeon et al. disclose wherein
in response to the signal differentiation having a first differentiation value, the read voltage level has a first value [Fig. 3: +Va], and
in response to the signal differentiation having a second differentiation value larger than the first differentiation value, the read voltage level has a second value [Fig. 3: -Va] smaller than the first value [Fig. 3: +Va].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) as applied to claim 1 above in view of Taylor et al. (US 20060250853).
Regarding claim 3, Jeon et al. teach the limitations with respect to claim 1.
However, Jeon et al. are silent with respect to further comprising:
sensing the bit line by a converter; and
determining the read voltage level according to a sensing resolution of the converter.
Taylor et al. teach further comprising:
sensing the bit line by a converter [Fig. 1: 120, para. 24-25]; and
determining the read voltage level according to a sensing resolution of the converter [pre-charging a reference voltage of 0.5V to the bit line near the comparator 122, para. 25. Taylor et al. also disclose accurately measures flash memory cell current (para. 36-37) and state the measurement accuracy is directly proportional to the length of the sensing time, para. 38].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Taylor et al. to the teaching of Jeon et al. such that choosing Jeon et al.’s read voltage as a function of the available resolution as taught by Taylor et al.; if the resolution is limited, using a higher read voltage; if the resolution is increased, using a lower read voltage to reduce disturb.
Regarding claim 4, Jeon et al. in combination with Taylor et al. teach the limitations with respect to claim 3.
Furthermore, Taylor et al. disclose when the converter has a first sensing resolution, the read voltage level has a first value, and
when the converter has a second sensing resolution higher than the first sensing resolution, the read voltage level has a second value lower than the first value [Taylor et al. describe that higher resolution resolves smaller bit line signal, para. 36 -38].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) as applied to claim 1 above and in view of Roohparvar (US 6327202).
Regarding claim 8, Jeon et al. teach the limitations with respect to claim 1.
However, Jeon et al. are silent with respect to when a cell number of the bit line is increased, the read voltage level is decreased.
Roohparvar teaches when a cell number of the bit line is increased, the read voltage level is decreased [Roohparvar discloses to achieve a pre-charge voltage of Vcc/4, Vcc/3 or Vcc/2, the global bit lines are coupled to 3, 2 or 1 local bit lines. The local bit lines are coupled to the global bit lines in response to the selected local bit line that contains the memory cell to be read, col. 7, lines 18-23. A lower pre-charge level reduces a voltage coupled to the memory cells of the local bit lines, col. 9, lines 45-46].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Roohparvar to the teaching of Jeon et al. such that applying technique of lowering the read voltage when a cell number of the bit line is increased as taught by Roohparvar to help provide fast simultaneous data reads of multiple columns of non-volatile memory cells [see Roohparvar’s col. 5, lines 1-2].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) as applied to claim 1 above in view of Eaton, Jr. (US 4873664).
Regarding claim 9, Jeon et al. teach the limitations with respect to claim 1.
However, Jeon et al. are silent with respect to the read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level.
Eaton, Jr. teaches the read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level [Eaton, Jr. disclose read voltage is 2.5 V (col. 2, lines 43-48) and coercive voltage is between 3V and 4V (col. 2, lines 24-26)].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Eaton, Jr. to the teaching of Jeon et al. such that applying a read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level as taught by Eaton, Jr. to Jeon et al.’s bit line to get predictable result and balance disturb.
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) in view of Kim et al. (US 20020196653).
Regarding independent claim 10, Jeon et al. disclose a memory device [Fig. 4], comprising:
a first memory cell configured to store a data bit [col. 5, lines 50-55];
a converter [Fig. 4: 100] configured to read the data bit [col. 5, lines 32-35];
a first bit line [Fig. 4: BL1] coupled between the first memory cell and the converter [see Fig. 4],
wherein the first memory cell comprises a first switch [Fig. 4: N0] and a first memory element [Fig. 4: C0],
during a read operation, the first bit line is charged to a read voltage level [see Fig. 2, the first bit line BL1 then transitions from a precharged level to one of two levels 88 or 66, col. 2, lines 30-32], and
the read voltage level is smaller than a coercive voltage level of the first memory element [see Fig. 3, col. 4, lines 26-29];
a plate line [Fig. 4: PL1] coupled to the first memory element [Fig. 4: C0]; and
a first word line [Fig. 4: WL1] coupled to a control terminal of the first switch [Fig. 4: N0].
However, Jeon et al. are silent with respect to wherein along a direction, the first bit line is disposed above the first word line, and the plate line is disposed above the first bit line.
Kim et al. teach wherein along a direction, the first bit line [Fig. 12: 71] is disposed above the first word line [Fig. 12: 57], and the plate line [Fig. 12: 87] is disposed above the first bit line [Fig. 12: 71, para. 47-48].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Eaton, Jr. to the teaching of Jeon et al. such that implementing the nondestructive read cell of Jeon et al. using the 3D ferroelectric bit cell layout of Kim et al. to obtain a predictable integrated FeRAM structure with known BL/WL/PL routing and reduced disturb.
Regarding claim 11, Jeon et al. in combination with Kim et al. teach the limitations with respect to claim 10.
Furthermore, Jeon et al. disclose when a voltage difference between two terminals of the first memory element is approximately equal to the coercive voltage level, a polarization of the first memory element is approximately equal to zero [see Fig. 3].
Regarding claim 12, Jeon et al. in combination with Kim et al. teach the limitations with respect to claim 11.
Furthermore, Jeon et al. disclose further comprising:
a second memory cell coupled to the first bit line [Fig. 4: BL1] and comprising a second switch [Fig. 4: N1] and a second memory element [Fig. 4: C1],
wherein the plate line [Fig. 4: PL1] is coupled to each of the first memory element and the second memory element [Fig. 4: N0], and maintained at a ground voltage level during the read operation [see Fig. 4].
Regarding claim 13, Jeon et al. in combination with Kim et al. teach the limitations with respect to claim 12.
Furthermore, Jeon et al. disclose further comprising:
a second word line [Fig. 4: WLm] coupled to a control terminal of the second switch [Fig. 4: N1],
wherein the first bit line [Fig. 4: BL1] is located between the plate line [Fig. 4: PL1] and each of the first word line [Fig. 4: WL1] and the second word line [Fig. 4: WLm].
Regarding claim 14, Jeon et al. in combination with Kim et al. teach the limitations with respect to claim 13.
Furthermore, Jeon et al. disclose further comprising:
a third memory cell coupled to the plate line [Fig. 4: PL1] and the first word line [Fig. 4: WL1]; and
a second bit line [Fig. 4: BLn] coupled to the third memory cell and having the read voltage level during the read operation [col. 5, lines 13-17].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) in view of Kim et al. (US 20020196653) as applied to claim 11 above, and further in view of Taylor et al. (US 20060250853).
Regarding claim 15, Jeon et al. in combination with Kim et al. teach the limitations with respect to claim 11 above.
However, Jeon et al. in combination with Kim et al. are silent with respect to when a sensing resolution of the converter is increased, the read voltage level is decreased.
Taylor et al. teach when a sensing resolution of the converter is increased, the read voltage level is decreased [Taylor et al. describe that higher resolution resolves smaller bit line signal, para. 36 -38].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Taylor et al. to the teaching of Jeon et al. in combination with Kim et al. such that choosing Jeon et al.’s read voltage as a function of the available resolution as taught by Taylor et al.; if the resolution is limited, using a higher read voltage; if the resolution is increased, using a lower read voltage to reduce disturb.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) in view of Kim et al. (US 20020196653) and Taylor et al. (US 20060250853) as applied to claim 15 above and further in view of Eaton, Jr. (US 4873664).
Regarding claim 16, Jeon et al. in combination with Kim et al. and Taylor et al. teach the limitations with respect to claim 15.
However, Jeon et al. in combination with Kim et al. and Taylor et al. are silent with respect to the read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level.
Eaton, Jr. teaches the read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level [Eaton, Jr. disclose read voltage is 2.5 V (col. 2, lines 43-48) and coercive voltage is between 3V and 4V (col. 2, lines 24-26)].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Eaton, Jr. to the teaching of Jeon et al. in combination with Kim et al. and Taylor et al. such that applying a read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level as taught by Eaton, Jr. to Jeon et al. in combination with Kim et al. and Taylor et al.’s bit line to get predictable result and balance disturb.
Claims 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) in view of Suzuki (US 20060215438).
Regarding independent claim 17, Jeon et al. disclose a method, comprising:
storing a data bit by a memory element [Fig. 4: CO, col. 5, lines 50-55];
charging a bit line to a read voltage level [see Fig. 2, the first bit line BL1 then transitions from a precharged level to one of two levels 88 or 66, col. 2, lines 30-32];
turning on a switch [Fig. 4: N0] coupled between the memory element [Fig. 4: C0] and the bit line [Fig. 4: BL1] by a word line [Fig. 4: WL1]; and
after the switch is turned on, sensing the bit line by a converter [Fig. 4: 100, col. 5, lines 32-35],
wherein the read voltage level is smaller than a voltage level [see Fig. 3, col. 4, lines 26-29],
when a voltage difference between two terminals of the memory element is approximately equal to the voltage level, a polarization of the memory element is approximately equal to zero [see Fig. 3].
However, Jeon et al. are silent with respect to the bit line is maintained at the read voltage level when the word line is changed from a first voltage level lower than the read voltage level to a second voltage level higher than the read voltage level.
Suzuki teaches a method comprising the bit line is maintained at the read voltage level when the word line is changed from a first voltage level lower than the read voltage level to a second voltage level higher than the read voltage level [see Fig. 3, when the bit lines BL and BLX become a floating state in a state precharged to a precharging voltage VPR, the selected word line WL is changed to a boosted voltage VPP (FIG. 3 (d)), para. 47].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Suzuki to the teaching of Jeon et al. such that applying Suzuki’s bit line precharge and word line boosting to the nondestructive read method of Jeon et al. to provide a stable read voltage on the bit line before cell coupling, reduce read disturb and prevent polarization reversal.
Regarding claim 19, Jeon et al. in combination with Suzuki teach the limitations with respect to claim 17.
Furthermore, Jeon et al. disclose further comprising:
calculating a signal differentiation of the memory element according to a first polarization [Fig. 3: point B], a second polarization [Fig. 3: point E], a third polarization [Fig. 3: point A] and a fourth polarization [Fig. 3: point C]; and
decreasing the read voltage level when the signal differentiation is increased [col. 4, lines 33-46],
wherein each of the first polarization and the second polarization corresponds to a first logic value [col. 4, lines 47-58],
each of the third polarization and the fourth polarization corresponds to a second logic value different from the first logic value [col. 4, lines 47-58],
each of the first polarization [Fig. 4: point B] and the third polarization [Fig. 4: point A] corresponds to the voltage difference being a zero voltage level [see Fig. 3], and
each of the second polarization [Fig. 4: point E] and the fourth polarization [Fig. 4: point C] corresponds to the voltage difference being the read voltage level [see Fig. 3].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) in view of Suzuki (US 20060215438) as applied to claim 17 above, and further in view of Taylor et al. (US 20060250853).
Regarding claim 18, Jeon et al. in combination with Suzuki teach the limitations with respect to claim 17 above.
However, Jeon et al. in combination with Suzuki are silent with respect to decreasing the read voltage level when a sensing resolution of the converter is increased.
Taylor et al. teach decreasing the read voltage level when a sensing resolution of the converter is increased [Taylor et al. describe that higher resolution resolves smaller bit line signal, para. 36 -38].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Taylor et al. to the teaching of Jeon et al. in combination with Suzuki such that choosing Jeon et al.’s read voltage as a function of the available resolution as taught by Taylor et al.; if the resolution is limited, using a higher read voltage; if the resolution is increased, using a lower read voltage to reduce disturb.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) in view of Suzuki (US 20060215438) as applied to claim 19 above, and further in view of Lee et al. (US 20220285374).
Regarding claim 20, Jeon et al. in combination with Suzuki teach the limitations with respect to claim 19.
However, Jeon et al. in combination with Suzuki are silent with respect to the signal differentiation is changed according to at least one of a thickness of a memory structure in the memory element, a composition of the memory structure and interfaces of the memory element.
Lee et al. teach the signal differentiation is changed according to at least one of a thickness of a memory structure in the memory element, a composition of the memory structure and interfaces of the memory element [thickness of the ferroelectric layers 106 may be used to increase the polarization difference, para. 25 and 35].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Lee et al. to the teaching of Jeon et al. in combination with Suzuki such that adjusting thickness of a memory structure in the memory element as taught by Lee et al. to change Jeon et al.’s signal differentiation to get predictable result and balance disturb.
Response to Arguments
Applicant's arguments filed on February 3, 2026 with respect to claim 1 have been fully considered but they are not persuasive.
With respect to independent claim 1, Applicant asserted that Jeon fails to teach that increasing the precharged level of BL1 when the magnitude of dQ1 versus dQ0 is decreased. Accordingly, Jeon fails to teach the limitations of "increasing the read voltage level when the signal differentiation is decreased" as explicitly recited in claim 1. Without teachings of "increasing the read voltage level when the signal differentiation is decreased", Jeon certainly fails to teach the limitations of "calculating a signal differentiation according to a first polarization difference and a second polarization difference of the memory element, wherein the first polarization difference and the second polarization difference correspond to a first logic value and a second logic value, respectively; and increasing the read voltage level when the signal differentiation is decreased" as explicitly recited in claim 1, see Applicant’s Remarks pages 17-18. This particular remark is not considered persuasive.
Jeon et al. teach measurement of the magnitude of dQ1 versus dQ0 can be performed by monitoring the induced potential on the bit line upon application of the read pulse (col. 4, lines 51-54). Moreover, Jeon et al.’s Fig. 3 teaches the measurable bit line signal differentiation is a function of the sub-coercive read pulse magnitude (col. 4, lines 39-49). Therefore, under MPEP 2112, the claimed increasing of read voltage when signal differentiation decreases is an inherent result of operating the disclosed nondestructive ferroelectric read system to obtain the disclosed measurable dQ1/dQ0 read distinction.
For the above reason, the previously applied rejection is considered proper and maintained.
Applicant’s arguments with respect to claims 10 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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Applicant’s attention is directed to the following reference: Tsukamoto (US 20240069869), which shows, in the Figure below, a 1T1FeC memory cell array used for multiply-accumulate operations, where the column of memory cells is connected to an analog-to-digital converter (ADC).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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