DETAILED ACTION
This action is responsive to the following communications: the Request for Continued Examination filed on September 16, 2026.
Claims 1-20 are pending. Claims 1, 10 and 17 are amended. Claims 1, 10 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 16, 2026 has been entered.
Claim Objections
Claims 1 and 10 are objected to because of the following informalities:
In claim 1, line 15, “a first voltage level high than” should be --a first voltage level higher than--.
In claim 10, lines 12-13, “and operate as a part of” should be --and operated as a part of--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400), in view of Dokania et al. (US 11482270).
Regarding independent claim 1, Jeon et al. disclose a method [Fig. 3], comprising:
charging a bit line to a read voltage level [see Fig. 2, the first bit line BL1 then transitions from a precharged level to one of two levels 88 or 66, col. 2, lines 30-32];
coupling the bit line [Fig. 4: BL1] to a memory element [Fig. 4: C0];
adjusting a voltage level of the bit line from the read voltage level according to a data bit stored in the memory element [see Fig. 2, depending on the value of the data (i.e., logic 1 or logic 0) stored in the ferroelectric capacitor 104, the first bit line BL1 then transitions from a precharged level to one of two levels 88 or 66, col. 2, lines 29-32];
calculating a signal differentiation according to a first polarization difference [Fig. 3: dQ1] and a second polarization difference [Fig. 3: dQ0] of the memory element [col. 4, lines 51-58], wherein the first polarization difference and the second polarization difference correspond to a first logic value and a second logic value, respectively [col. 4, lines 47-58];
and increasing the read voltage level when the signal differentiation is decreased [Jeon et al. teach measurement of the magnitude of dQ1 versus dQ0 can be performed by monitoring the induced potential on the bit line upon application of the read pulse (col. 4, lines 51-54). Moreover, Jeon et al.’s Fig. 3 teaches the measurable bit line signal differentiation is a function of the sub-coercive read pulse magnitude (col. 4, lines 47-49). Therefore, under MPEP 2112, the claimed increasing of read voltage when signal differentiation decreases is an inherent result of operating the disclosed nondestructive ferroelectric read system to obtain the disclosed measurable dQ1/dQ0 read distinction],
wherein the read voltage level [Fig. 3: -Va] is smaller than a coercive voltage level [Fig. 3: -Vc] of the memory element [col. 4, lines 26-29];
receiving a plate line signal by the memory element [see Fig. 4, col. 4, lines 62-66 as well as col. 5, lines 26-29],
in response to writing the second logic value to the memory element, maintaining the bit line at a first voltage level higher than the coercive voltage level throughout a period [see Fig. 8, col. 7, lines 36-49].
However, Jeon et al. are silent with respect to within the period, changing the plate line signal from a ground voltage level to the first voltage level and changing the plate line signal from the first voltage level to the ground voltage level.
Dokania et al. teach in response to writing the second logic value to the memory element, maintaining the bit line at a first voltage level throughout a period [see Fig. 10C, BLx is pulsed to Vdd to write a logic 1, col. 44, lines 45-59]; and
within the period, changing the plate line signal from a ground voltage level to the first voltage level and changing the plate line signal from the first voltage level to the ground voltage level [see Fig. 10C, PL0 is pulsed within a pulse width of BLx during a logic write 1 operation, col. 44, lines 58-59].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Dokania et al. to the teaching of Jeon et al. such that modifying the ferroelectric memory method of Jeon et al. using the programmable bit line and write pulse techniques as taught by Dokania et al., in which the bit line is maintained high while the plate line transitions from ground to a high level and back to ground, to reduce write disturbance and improve reliability.
Regarding claim 2, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 1.
Furthermore, Jeon et al. disclose when a voltage difference between two terminals of the memory element is approximately equal to the coercive voltage level, a polarization of the memory element is approximately equal to zero [see Fig. 3].
Regarding claim 5, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 1.
Furthermore, Jeon et al. disclose further comprising:
determining the read voltage level according to the signal differentiation [col. 4, lines 33-46],
wherein the first logic value and the second logic value are different from each other [col. 4, lines 47-58].
Regarding claim 6, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 5.
Furthermore, Jeon et al. disclose wherein
the first polarization difference [Fig. 3: dQ0] is a difference between a first polarization [Fig. 4: point B] and a second polarization [Fig. 4: point E],
the second polarization difference [Fig. 3: dQ1] is a difference between a third polarization [Fig. 3: point A] and a fourth polarization [Fig. 3: point C],
each of the first polarization [Fig. 4: point B] and the third polarization [Fig. 4: point A] corresponds to a zero voltage level [see Fig. 4], and
each of the second polarization [Fig. 4: point C] and the fourth polarization [Fig. 4: point E] corresponds to the read voltage level [see Fig. 4].
Regarding claim 7, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 6.
Furthermore, Jeon et al. disclose wherein
in response to the signal differentiation having a first differentiation value, the read voltage level has a first value [Fig. 3: +Va], and
in response to the signal differentiation having a second differentiation value larger than the first differentiation value, the read voltage level has a second value [Fig. 3: -Va] smaller than the first value [Fig. 3: +Va].
Regarding independent claim 10, Jeon et al. disclose a memory device [Fig. 4], comprising:
a first memory cell configured to store a data bit [col. 5, lines 50-55];
a converter [Fig. 4: 100] configured to read the data bit [col. 5, lines 32-35];
a first bit line [Fig. 4: BL1] coupled between the first memory cell and the converter [see Fig. 4],
wherein the first memory cell comprises a first switch [Fig. 4: N0] and a first memory element [Fig. 4: C0],
during a read operation, the first bit line is charged to a read voltage level [see Fig. 2, the first bit line BL1 then transitions from a precharged level to one of two levels 88 or 66, col. 2, lines 30-32], and
the read voltage level is smaller than a coercive voltage level of the first memory element [see Fig. 3, col. 4, lines 26-29];
a plate line [Fig. 4: PL1] coupled to the first memory element [Fig. 4: C0]; and
a first word line [Fig. 4: WL1] coupled to a control terminal of the first switch [Fig. 4: N0].
However, Jeon et al. are silent with respect to wherein along a direction, the first bit line is disposed above the first word line, and the plate line is disposed above the first bit line; and an electrode portion coupled to the plate line, elongated along the direction, and operate as a part of the first memory element.
Dokania et al. teach wherein along a direction, the first bit line [Fig. 4C: 310] is disposed above the first word line [Fig. 4C: 317], and the plate line [Fig. 4C: 315] is disposed above the first bit line [Fig. 4C: 310, col. 25, lines 66-67 and col. 26, lines 1-4] and an electrode portion [Fig. 4C: 400 with respect to Fig. 4A, col. 24, lines 49-67 and col. 25, lines 1-35], coupled to the plate line [Fig. 4C: 315], elongated along the direction, and operated as a part of the first memory element [see Fig. 4C with respect to Fig. 4A, Fig. 4C illustrates various 3D view of memory bit-cells with planar or non-planar transistors, and with non-planar (or pillar) capacitor, col. 25, lines 54-57].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Dokania et al. to the teaching of Jeon et al. such that implementing the nondestructive read cell of Jeon et al. using the 3D memory cell structure as taught by Dokania et al. to obtain a predictable integrated FeRAM structure with known BL/WL/PL/electrode routing and reduce layout area while retaining Jeon et al.’s nondestructive read operation.
Regarding claim 11, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 10.
Furthermore, Jeon et al. disclose when a voltage difference between two terminals of the first memory element is approximately equal to the coercive voltage level, a polarization of the first memory element is approximately equal to zero [see Fig. 3].
Regarding claim 12, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 11.
Furthermore, Jeon et al. disclose further comprising:
a second memory cell coupled to the first bit line [Fig. 4: BL1] and comprising a second switch [Fig. 4: N1] and a second memory element [Fig. 4: C1],
wherein the plate line [Fig. 4: PL1] is coupled to each of the first memory element and the second memory element [Fig. 4: N0], and maintained at a ground voltage level during the read operation [see Fig. 4].
Regarding claim 13, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 12.
Furthermore, Jeon et al. disclose further comprising:
a second word line [Fig. 4: WLm] coupled to a control terminal of the second switch [Fig. 4: N1],
wherein the first bit line [Fig. 4: BL1] is located between the plate line [Fig. 4: PL1] and each of the first word line [Fig. 4: WL1] and the second word line [Fig. 4: WLm].
Regarding claim 14, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 13.
Furthermore, Jeon et al. disclose further comprising:
a third memory cell coupled to the plate line [Fig. 4: PL1] and the first word line [Fig. 4: WL1]; and
a second bit line [Fig. 4: BLn] coupled to the third memory cell and having the read voltage level during the read operation [col. 5, lines 13-17].
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) in view of Dokania et al. (US 11482270) as applied to claim 1 above, and further in view of Taylor et al. (US 20060250853).
Regarding claim 3, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 1.
However, Jeon et al. in combination with Dokania et al. are silent with respect to further comprising:
sensing the bit line by a converter; and
determining the read voltage level according to a sensing resolution of the converter.
Taylor et al. teach further comprising:
sensing the bit line by a converter [Fig. 1: 120, para. 24-25]; and
determining the read voltage level according to a sensing resolution of the converter [pre-charging a reference voltage of 0.5V to the bit line near the comparator 122, para. 25. Taylor et al. also disclose accurately measures flash memory cell current (para. 36-37) and state the measurement accuracy is directly proportional to the length of the sensing time, para. 38].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Taylor et al. to the teaching of Jeon et al. in combination with Dokania et al. such that choosing Jeon et al.’s read voltage as a function of the available resolution as taught by Taylor et al.; if the resolution is limited, using a higher read voltage; if the resolution is increased, using a lower read voltage to reduce disturb.
Regarding claim 4, Jeon et al. in combination with Dokania et al. and Taylor et al. teach the limitations with respect to claim 3.
Furthermore, Taylor et al. disclose when the converter has a first sensing resolution, the read voltage level has a first value, and
when the converter has a second sensing resolution higher than the first sensing resolution, the read voltage level has a second value lower than the first value [Taylor et al. describe that higher resolution resolves smaller bit line signal, para. 36 -38].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) in view of Dokania et al. (US 11482270) as applied to claim 1 above, and further in view of Roohparvar (US 6327202).
Regarding claim 8, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 1.
However, Jeon et al. in combination with Dokania et al. are silent with respect to when a cell number of the bit line is increased, the read voltage level is decreased.
Roohparvar teaches when a cell number of the bit line is increased, the read voltage level is decreased [Roohparvar discloses to achieve a pre-charge voltage of Vcc/4, Vcc/3 or Vcc/2, the global bit lines are coupled to 3, 2 or 1 local bit lines. The local bit lines are coupled to the global bit lines in response to the selected local bit line that contains the memory cell to be read, col. 7, lines 18-23. A lower pre-charge level reduces a voltage coupled to the memory cells of the local bit lines, col. 9, lines 45-46].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Roohparvar to the teaching of Jeon et al. in combination with Dokania et al. such that applying technique of lowering the read voltage when a cell number of the bit line is increased as taught by Roohparvar to help provide fast simultaneous data reads of multiple columns of non-volatile memory cells [see Roohparvar’s col. 5, lines 1-2].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) in view of Dokania et al. (US 11482270) as applied to claim 1 above, and further in view of Eaton, Jr. (US 4873664).
Regarding claim 9, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 1.
However, Jeon et al. in combination with Dokania et al. are silent with respect to the read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level.
Eaton, Jr. teaches the read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level [Eaton, Jr. disclose read voltage is 2.5 V (col. 2, lines 43-48) and coercive voltage is between 3V and 4V (col. 2, lines 24-26)].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Eaton, Jr. to the teaching of Jeon et al. in combination with Dokania et al. such that applying a read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level as taught by Eaton, Jr. to Jeon et al.’s bit line to get predictable result and balance disturb.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) in view of Dokania et al. (US 11482270) as applied to claim 11 above, and further in view of Taylor et al. (US 20060250853).
Regarding claim 15, Jeon et al. in combination with Dokania et al. teach the limitations with respect to claim 11 above.
However, Jeon et al. in combination with Dokania et al. are silent with respect to when a sensing resolution of the converter is increased, the read voltage level is decreased.
Taylor et al. teach when a sensing resolution of the converter is increased, the read voltage level is decreased [Taylor et al. describe that higher resolution resolves smaller bit line signal, para. 36 -38].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Taylor et al. to the teaching of Jeon et al. in combination with Dokania et al. such that choosing Jeon et al.’s read voltage as a function of the available resolution as taught by Taylor et al.; if the resolution is limited, using a higher read voltage; if the resolution is increased, using a lower read voltage to reduce disturb.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 5835400) in view of Dokania et al. (US 11482270) and Taylor et al. (US 20060250853) as applied to claim 15 above and further in view of Eaton, Jr. (US 4873664).
Regarding claim 16, Jeon et al. in combination with Dokania et al. and Taylor et al. teach the limitations with respect to claim 15.
However, Jeon et al. in combination with Dokania et al. and Taylor et al. are silent with respect to the read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level.
Eaton, Jr. teaches the read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level [Eaton, Jr. disclose read voltage is 2.5 V (col. 2, lines 43-48) and coercive voltage is between 3V and 4V (col. 2, lines 24-26)].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Eaton, Jr. to the teaching of Jeon et al. in combination with Dokania et al. and Taylor et al. such that applying a read voltage level is within a range from 0.3 times the coercive voltage level to 0.8 times the coercive voltage level as taught by Eaton, Jr. to Jeon et al. in combination with Dokania et al. and Taylor et al.’s bit line to get predictable result and balance disturb.
Allowable Subject Matter
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 17, there is no teaching or suggestion either alone or in combination in the prior art of record to provide the recited a method comprising turning on a switch coupled between the memory element and the bit line by a word line; and after the switch is turned on, sensing the bit line by a converter, wherein the read voltage level is smaller than a voltage level, when a voltage difference between two terminals of the memory element is approximately equal to the voltage level, a polarization of the memory element is approximately equal to zero, the bit line is maintained at the read voltage level when the word line is changed from a first voltage level lower than the read voltage level to a second voltage level higher than the read voltage level, and a period of the bit line maintained at the read voltage level is longer than a period of the word line maintained at the second voltage level, in combination with other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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