DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 5- are rejected under 35 U.S.C. 102(1)(1) as being anticipated by Kim et al. (PG Pub. No. US 2020/0402817 A1).
Regarding claim 5, Kim teaches a method for forming a semiconductor device (fig. 2o), comprising:
providing a substrate (¶ 0021: 120);
attaching a first set of electronic components (¶ 0023: 104/130 in region 140a) and a second set of electronic components (104/130 in region 140b) onto the substrate (figs. 2c-2d: first and second sets of 104/130 attached on 120);
attaching a first external connector (¶ 0027 & fig. 2g: left-most 142) onto a first side of the first and second sets of electronic components (fig. 2g: 142 attached on left side of 104/130);
attaching a second external connector (right-most 142) onto a second side of the first and second sets of electronic components (fig. 2g: 142 attached on right side of 104/130), wherein the first side and the second side are two opposite outer sides of the first and second sets of electronic components (fig. 2g: 142 attached on laterally opposing sides of 104/130);
forming a common encapsulant layer (¶ 0029: 146) on the substrate to cover the first and second sets of electronic components but expose the first and second external connectors (fig. 2k: 146 formed on 120, covers both sets of 104/130, and exposes left-most and right-most 142), wherein the common encapsulant laver covers a region between the first and second sets of electronic components (fig. 2k: 146 covers region between first and second sets of 104/130); and
singulating the substrate and the encapsulant layer at a saw street within the region between the first and second sets of electronic components (¶ 0030 & figs. 2h, 2m: 120 and 146 singulated by 148 at saw street 144 between sets of 104/130) to separate the first set of electronic components and the first external connector from the second set of electronic components and the second external connector (fig. 2m: sets of 104/130 separated into modules 150).
PNG
media_image1.png
262
612
media_image1.png
Greyscale
Regarding claim 6, Kim teaches the method of claim 5, further comprising:
forming a shielding layer on each of the encapsulant layers covering the first set of electronic components and the second set of electronic components (¶ 0032: 154 formed on 146 of each module 150).
Regarding claim 7, Kim teaches the method of claim 5, wherein the first set of electronic components and the first external connector are identical to and symmetrically disposed on the substrate to the second set of electronic components and the second external connector with respect to the saw street (figs. 2h, 2k among others: sets of 104/130 arranged in translational symmetry with respect to saw street 144).
Regarding claim 8, Kim teaches the method of claim 5, wherein the first and second external connectors are board-to-board connectors (fig. 7 among others: 142 configured to connect to PCB 202, meeting the broadest reasonable interpretation of “board-to-board connectors”).
Regarding claim 9, Kim teaches the method of claim 5, wherein each of the first and second sets of electronic components comprises at least one semiconductor die (¶ 0016: at least 104 comprises semiconductor die).
Regarding claim 10, Kim teaches a semiconductor device (fig. 2o), formed by a method comprising the following steps:
providing a substrate (¶ 0021: 120);
attaching a first set of electronic components (¶ 0023: 104/130 in region 140a) and a second set of electronic components (104/130 in region 140b) onto the substrate (figs. 2c-2d: first and second sets of 104/130 attached on 120);
attaching a first external connector (¶ 0027 & fig. 2g: left-most 142) onto a first side of the first and second sets of electronic components (fig. 2g: 142 attached on left side of 104/130);
attaching a second external connector (right-most 142) onto a second side of the first and second sets of electronic components (fig. 2g: 142 attached on right side of 104/130), wherein the first side and the second side are two opposite outer sides of the first and second sets of electronic components (fig. 2g: 142 attached on laterally opposing sides of 104/130);
forming a common encapsulant layer (¶ 0029: 146) on the substrate to cover the first and second sets of electronic components but expose the first and second external connectors (fig. 2k: 146 formed on 120, covers both sets of 104/130, and exposes left-most and right-most 142), wherein the common encapsulant laver covers a region between the first and second sets of electronic components (fig. 2k: 146 covers region between first and second sets of 104/130); and
singulating the substrate and the encapsulant layer at a saw street within the region between the first and second sets of electronic components (¶ 0030 & figs. 2h, 2m: 120 and 146 singulated by 148 at saw street 144 between sets of 104/130) to separate the first set of electronic components and the first external connector from the second set of electronic components and the second external connector (fig. 2m: sets of 104/130 separated into modules 150).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (PG Pub. No. US 2020/0075502 A1, hereinafter referenced as ‘Kim-502’) in view of Choi (PG Pub. No. US 2021/0217700 A1).
Regarding claim 1, Kim-502 teaches a semiconductor package strip (¶ 0021 & figs. 2b-2c: 100), comprising:
a substrate (¶ 0021: 110);
a first semiconductor package including a first set of electronic components (¶¶ 0006, 0024: first package including 52 and/or 124) and a first external connector (¶ 0028: 114/116/150, external to 130) attached on the substrate (figs. 2b-2c: 52/124 and/or 114/116/150 attached on 110);
a second semiconductor package including a second set of electronic components (second package including 52 and/or 124) and a second external connector (second 114/116/150, external to 130) attached on the substrate (figs. 2b-2c: 52/124 and 114/116/150 attached on 110);
wherein the first and second external connectors are disposed at two opposite outer sides of the first and second sets of electronic components, respectively (figs. 2b-2c: 114/116/150 disposed at opposite outer sides of at least 52 of first package and 124 of second package);
a common encapsulant layer (¶ 0025: 130) formed on the substrate (figs. 2b-2c: 130 formed on 110), wherein the common encapsulant layer covers the first and second sets of electronic components but exposes the first and second external connectors (figs. 2b-2c: 130 covers first 52/124 and second 52/124, and exposes first and second 114/116/150), and the common encapsulant laver covers a region between the first and second sets of electronic components (figs. 2b-2c: 130 covers a portion of 110 between first and second 52/124); and
a saw street (¶ 0021: 102) within the region between the first and second sets of electronic components that allows for singulation of the semiconductor package strip at the saw street (figs. 2c-2d: 102 between 52 of first package and 124 of second package to allow singulation).
Kim-502 does not explicitly teach wherein the first set of electronic components are adjacent to the second set of electronic components.
Choi teaches a first and second semiconductor packages (¶ 0031: 300, 400), wherein connectors (¶¶ 0046, 0054: 330, 430) are disposed at one side of each package (figs. 3-4: 330 disposed at one side of 300, 430 disposed at one side of 400).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the package strip of Kim-502 such that the first set of electronic components are adjacent to the second set of electronic components, as a means to provide packages with connectors on one side of each package, allowing for arranging packages in a stacked configuration, increasing package density and producing high performance semiconductor packages that process a large amount of data at a high speed.
Furthermore, it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japiske, 86 USPQ 70. In the instant case, re-arranging the first set of electronic components of Kim to be adjacent to the second set of electronic components involved only routine skill.
PNG
media_image2.png
264
770
media_image2.png
Greyscale
Regarding claim 2, Kim-502 in view of Choi teaches the semiconductor package strip of claim 1, wherein the first set of electronic components and the first external connector are identical to and symmetrically disposed on the substrate to the second set of electronic components and the second external connector with respect to the saw street (Kim-502, figs. 2g-2h & Choi, figs. 3-4: 52/124 and 114/116/150 identical in each package, and rearranged with the connector arrangement of Choi to be symmetrically disposed on 110).
Regarding claim 3, Kim-502 in view of Choi teaches the semiconductor package strip of claim 1, wherein the first and second external connectors are board-to-board connectors (Kim-502, ¶ 0034: at least 116 is a bump connector, suitable for connection between first and second boards, meeting the broadest reasonable interpretation of ‘board-to-board connectors’).
Regarding claim 4, Kim-502 in view of Choi teaches the semiconductor package strip of claim 1, wherein each of the first and second sets of electronic components comprises at least one semiconductor die (Kim-502, at least one of 52 and 124 of each package comprises a semiconductor die).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRIAN TURNER/ Examiner, Art Unit 2818
Prosecution Insights