DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-8, 17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20120025286 A1 Nojima hereafter “Nojima”.
Claim 1 Nojima teaches a method of forming a vertical transistor structure, the method comprising:
forming a source/drain region [see annotation below, illustrated fig. 2, explicitly disclosed Paragraph 0044 “upper contact 14 corresponding to a drain or a source is formed on the upper surface of silicon pillar 11”] and a channel [See annotation below, illustrated fig. 2] that are stacked in a vertical direction relative to a substrate (10 fig. 15); and
forming a junction [see annotation below, illustrated fig.2], wherein:
a cross-sectional diameter of the junction continuously varies in an increasing manner in the vertical direction from a cross-sectional diameter of the channel to a cross-sectional diameter of the source/drain region to connect the source/drain region to the channel without a stepwise transition between the cross-sectional diameter of the channel and the cross-sectional diameter of the source/drain region [sufficiently illustrated fig. 2].
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Annotated fig. 2: highlighting a source/drain, a channel and a junction
Claim 6 Nojima teaches the method of claim 1, further comprising:
forming a gate insulator (12 fig. 2) adjacent the channel; and
forming a gate (13 fig. 2) adjacent the gate insulator.
Claim 7 Nojima teaches as shown above the method of claim 1, further comprising forming a nanowire (11 fig. 2 wherein a silicon pillar on the nanometer scale is identical and/or the same as the disclosed the structure of a nanowire see MPEP 2112.01) that extends in the vertical direction.
Claim 8 Nojima teaches as shown above the method of claim 7, wherein a portion of the nanowire is embedded in the source/drain region (sufficiently illustrated fig. 2, under broadest reasonable interpretation wherein embedded includes the meaning “of a device or system: functioning as part of a larger device rather than as an independent unit or system” and the silicon pillar/nanowire is part of the source/drain region).
Claim 17 Nojima teaches a method of forming a vertical transistor structure, the method comprising:
forming a source/drain region [see annotation below, illustrated fig. 2, explicitly disclosed Paragraph 0044 “upper contact 14 corresponding to a drain or a source is formed on the upper surface of silicon pillar 11”] and a channel [See annotation below, illustrated fig. 2] that are stacked in a vertical direction relative to a substrate (10 fig. 2); and
forming a junction [See annotation below, illustrated fig. 2], wherein:
a cross-sectional diameter of the junction continuously varies in an increasing manner in the vertical direction from a cross-sectional diameter of the channel to a cross-sectional diameter of the source/drain region to connect the source/drain region to the channel [sufficiently illustrated fig. 2]; and
at least a portion of the source/drain region has a cross-sectional diameter that varies in an increasing manner away from the substrate [sufficiently disclosed paragraph 0044 “ in the present exemplary embodiment, the side surface of a tapered portion on which a source or a drain is formed (a lower portion of silicon pillar 11) is a Si{111} plane”, illustrated fig. 2].
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Annotated fig. 2: highlighting a source/drain, a channel and a junction
Claim 20 Nojima teaches as shown above the method of claim 17, further comprising:
forming a gate insulator (12 fig. 2) adjacent the channel; and
forming a gate (13 fig. 2) adjacent the gate insulator.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5, 9-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nojima as applied to the claims above, and further in view of US 20140001520 A1 Glass et al here after “Glass”.
Claim 2 Nojima teaches as shown above the method of claim 1,
Nojima does not teach at least one of the source/drain region and the channel has about 20-95 atomic percent of Sn.
Glass teaches a semiconductor layer comprising GeSn has about a Sn concentration up to 30 atomic percent (Sufficiently overlaps with about 20-95 atomic percent) and that the Sn concentration may be adjusted to tailor the valence band in order to minimize the energy barrier at its interfaces [sufficiently disclosed Paragraph 0018].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Surthi in view of Glass such that “at least one of the source/drain region and the channel has about 20-95 atomic percent of Sn”.
A person of ordinary skill in the art would have been motivated to make this modification as a part of routine optimization of the valence bands and/or energy barriers of the device [See MPEP 2144.05 II.]
In addition, the selection of a known material based on its suitability for its intended use is prima facie type obviousness [See MPEP 2144.07]. In this case its selection of GeSn with a specific Sn concentration.
Claim 3 Nojima teaches as shown above the method of claim 1, wherein the channel is semiconducting [sufficiently disclosed paragraph 0006 “a channel is produced in silicon pillar 101” under broadest reasonable interpretation of “channel” and/or active region of a semiconductor device]
Nojima does not teach the source/drain region is metallic.
Glass teaches “the bandgap for GeSn alloys starts at 0.66 eV for pure Ge, and becomes metallic (no bandgap) for high tin concentrations (approximately 30 atomic % Sn)” [explicitly disclosed paragraph 0012].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nojima in view of Glass such that “the source/drain region is metallic”.
A person of ordinary skill in the art would have been motivated to make this modification to enable tailoring of the band alignment between the GeSn alloy and the metal contact layer, which can create a near-zero energy barrier at the GeSn/contact metal interface, and/or improvement of the contact resistance [Glass explicitly discloses Paragraph 0012].
In addition, selection of a know material based on its suitability for its intended use is prima facie type obviousness. In this case is the selection of known metal and/or metallic materials for the source/drain region.
Claim 4 Nojima teaches as shown above the method of claim 1, a silicon pillar (11 fig. 2) comprising the channel and source/drain if formed with a diameter equal to a minimum feature size F (nm) [Paragraph 0034] and that “there has been a demand for reducing the chip area year by year for the purpose of achieving a low cost. To meet this demand, 4F2 (2F*2F) cell structures have been proposed” [Paragraph 0005]
Nojima does not teach the channel has a diameter of about 1-15 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nojima such that “the channel has a diameter of about 1-15 nanometers”.
A person of ordinary skill in the art would have been motivated to make this modification as a part of routine optimization to reduce the area of the chip and/or cell while maintain functionality and/or conductivity through an active region [See MPEP 2144.05 II.].
In addition, changes in size and/or relative dimensions is prima facie type obviousness [See MPEP 2144.04 IV. A.]
Claim 5 Nojima teaches as shown above the method of claim 1,
a silicon pillar (11 fig. 2) comprising the channel and source/drain if formed with a diameter equal to a minimum feature size F (nm) [Paragraph 0034] and that “there has been a demand for reducing the chip area year by year for the purpose of achieving a low cost. To meet this demand, 4F2 (2F*2F) cell structures have been proposed” [Paragraph 0005]
Nojima does not teach the source/drain has a diameter of about 5-30 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nojima such that “the source/drain has a diameter of about 5-30 nanometers”.
A person of ordinary skill in the art would have been motivated to make this modification as a part of routine optimization to reduce the area of the chip and/or cell while maintain functionality and/or conductivity through an active region [See MPEP 2144.05 II.].
In addition, changes in size and/or relative dimensions is prima facie type obviousness [See MPEP 2144.04 IV. A.]
Claim 9 Nojima teaches a method of forming a vertical transistor structure, the method comprising:
forming a source/drain region [see annotation below, illustrated fig. 2, explicitly disclosed Paragraph 0044 “upper contact 14 corresponding to a drain or a source is formed on the upper surface of silicon pillar 11”] and a channel [See annotation below, illustrated fig. 2], wherein the source/drain region and the channel are stacked in a vertical direction relative to a substrate (10 fig. 2)[sufficiently illustrated fig. 2]; and
forming a junction [see annotation below, sufficiently illustrated fig. 2], wherein a cross-sectional diameter of the junction continuously varies in an increasing manner in the vertical direction from a cross-sectional diameter of the channel to a cross-sectional diameter of the source/drain region to connect the source/drain region to the channel [sufficiently illustrated fig. 2].
Nojima does not teach the source/drain region mode of GeSn, SiSn, or SiGeSn; the channel made of GeSn, SiSn, or SiGeSn.
Glass teaches a semiconductor layer comprising GeSn has about a Sn concentration up to 30 atomic percent (Sufficiently overlaps with about 20-95 atomic percent) and that the Sn concentration may be adjusted to tailor the valence band in order to minimize the energy barrier at its interfaces [sufficiently disclosed Paragraph 0018].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Surthi in view of Glass such that the source/drain region mode of GeSn, SiSn, or SiGeSn; the channel made of GeSn, SiSn, or SiGeSn.
A person of ordinary skill in the art would have been motivated to make this modification as a part of routine optimization of the valence bands and/or energy barriers of the device [See MPEP 2144.05 II.]
In addition, the selection of a known material based on its suitability for its intended use is prima facie type obviousness [See MPEP 2144.07]. In this case its selection of GeSn with a specific Sn concentration.
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Annotated fig. 2: highlighting a source/drain, a channel and a junction
Claim 10 Nojima in view of Glass teach as shown above the method of claim 9, wherein at least one of the source/drain region and the channel has about 20-95 atomic percent of Sn [met in view of the modification of Glass as shown above].
Claim 11 Nojima in view of Glass teach the method of claim 9, wherein the source/drain region is metallic and the channel is semiconducting [met in view of Glass the material GeSn as shown above “the bandgap for GeSn alloys starts at 0.66 eV for pure Ge, and becomes metallic (no bandgap) for high tin concentrations (approximately 30 atomic % Sn)” explicitly disclosed paragraph 0012].
Claim 12 Nojima in view of Glass The method of claim 9
a silicon pillar (11 fig. 2) comprising the channel and source/drain if formed with a diameter equal to a minimum feature size F (nm) [Paragraph 0034] and that “there has been a demand for reducing the chip area year by year for the purpose of achieving a low cost. To meet this demand, 4F2 (2F*2F) cell structures have been proposed” [Paragraph 0005]
Nojima in view of Glass does not teach the source/drain has a diameter of about 5-30 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Nojima in view of Glass such that “the source/drain has a diameter of about 5-30 nanometers”.
A person of ordinary skill in the art would have been motivated to make this modification as a part of routine optimization to reduce the area of the chip and/or cell while maintain functionality and/or conductivity through an active region [See MPEP 2144.05 II.].
In addition, changes in size and/or relative dimensions is prima facie type obviousness [See MPEP 2144.04 IV. A.]
Claim 13 Nojima in view of Glass teaches as shown above the method of claim 9,
a silicon pillar (11 fig. 2) comprising the channel and source/drain if formed with a diameter equal to a minimum feature size F (nm) [Paragraph 0034] and that “there has been a demand for reducing the chip area year by year for the purpose of achieving a low cost. To meet this demand, 4F2 (2F*2F) cell structures have been proposed” [Paragraph 0005]
Nojima in view of Glass does not teach the channel has a diameter of about 1-15 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Nojima in view of glass such that “the channel has a diameter of about 1-15 nanometers”.
A person of ordinary skill in the art would have been motivated to make this modification as a part of routine optimization to reduce the area of the chip and/or cell while maintain functionality and/or conductivity through an active region [See MPEP 2144.05 II.].
In addition, changes in size and/or relative dimensions is prima facie type obviousness [See MPEP 2144.04 IV. A.].
Claim 14 Nojima in view of Glass teaches the method of claim 9, further comprising:
forming a gate insulator (12 fig. 2) adjacent the channel; and
forming a gate (13 fig. 2) adjacent the gate insulator.
Claim 15 Nojima in view of Glass The method of claim 9, further comprising forming a nanowire (11 fig. 2 wherein a silicon pillar on the nanometer scale is identical and/or the same as the disclosed the structure of a nanowire see MPEP 2112.01) that extends in the vertical direction.
Claim 16 Nojima in view of Glass teaches as shown above the method of claim 15, wherein a portion of the nanowire is embedded in the source/drain region (sufficiently illustrated fig. 2, under broadest reasonable interpretation wherein embedded includes the meaning “of a device or system: functioning as part of a larger device rather than as an independent unit or system” and the silicon pillar/nanowire is part of the source/drain region).
Claim 18 Nojima teaches as shown above the method of claim 17,
Nojima does not teach wherein at least one of the source/drain region and the channel has about 20-95 atomic percent of Sn.
Glass teaches a semiconductor layer comprising GeSn has about a Sn concentration up to 30 atomic percent (Sufficiently overlaps with about 20-95 atomic percent) and that the Sn concentration may be adjusted to tailor the valence band in order to minimize the energy barrier at its interfaces [sufficiently disclosed Paragraph 0018].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Surthi in view of Glass such that “at least one of the source/drain region and the channel has about 20-95 atomic percent of Sn”.
A person of ordinary skill in the art would have been motivated to make this modification as a part of routine optimization of the valence bands and/or energy barriers of the device [See MPEP 2144.05 II.]
In addition, the selection of a known material based on its suitability for its intended use is prima facie type obviousness [See MPEP 2144.07]. In this case its selection of GeSn with a specific Sn concentration.
Claim 19 Nojima teaches as shown above the method of claim 17,
wherein the channel is semiconducting [sufficiently disclosed paragraph 0006 “a channel is produced in silicon pillar 101” under broadest reasonable interpretation of “channel” and/or active region of a semiconductor device]
Nojima does not teach the source/drain region is metallic.
Glass teaches that source/drain maybe formed with p-type or n-type dopants [Paragraph 0017] and discloses metal and/or metallic p-type dopants Al, Ga, or In [Paragraph 0018].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nojima in view of Glass such that “the source/drain region is metallic”.
A person of ordinary skill in the art would have been motivated to make this modification to achieve a p-type conductivity for the source/drain region and/or the desired barrier and/or threshold voltage and/or energy.
In addition, selection of a known material based on its suitability for its intended use is prima facie type obviousness. In this case is the selection of known metal and/or metallic materials for the source/drain region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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