Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/19/2025, 08/28/2025 and 06/02/2026 have been considered by the examiner.
Oath/Declaration
Oath/Declaration as file 04/16/2024 is noted by the Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-14 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Wang et al. US 2016/0077147 (Provided by Applicant; Hereinafter Wang).
Regarding claim 1, Wang teaches a method for wafer measurement ([0011-0012]), comprising:
generating a first recipe ([0033]) for measuring a first part ([0032]) of a plurality of wafers ([0010]; “In semiconductor processing, dies or chips are formed in groups on wafers, permitting bulk processing of the dies…”);
generating a second recipe ([0033]) for measuring a second part ([0032]) of the plurality of wafers ([0010]; “In semiconductor processing, dies or chips are formed in groups on wafers, permitting bulk processing of the dies…”);
generating a measurement program ([0014]) associated with the first recipe ([0033]) and the second recipe ([0033]); and
controlling ([0014-0019]) a measurement device ([0016]), by executing the measurement program ([0014]), to measure the first part ([0032]) of the plurality of wafers ([0010]) and the second part ([0032]) of the plurality of wafers ([0010]) according to the first recipe ([0033]) and the second recipe ([0033]) respectively ([0010-0012, 0014-0019, 0032-0033, 0042]).
Regarding claim 2, Wang further teaches the method of claim 1, wherein the first recipe includes a plurality of first parameters corresponding to the first part of the plurality of wafers ([0022]).
Regarding claim 3, Wang further teaches the method of claim 2, wherein the plurality of first parameters correspond to a first semiconductor device of the first part of the plurality of wafers ([0011]).
Regarding claim 4, Wang further teaches the method of claim 3, wherein the plurality of first parameters includes at least one of a first probe pattern of probes of the measurement device ([0020, 0023, 0025, 0037]), a first measurement algorithm and a first measurement temperature ([0020, 0023, 0025, 0037]).
Regarding claim 5, Wang further teaches the method of claim 4, wherein the first probe pattern corresponds to contacts of the first semiconductor device ([0022]).
Regarding claim 6, Wang further teaches the method of claim 5, wherein the first measurement algorithm corresponds to a first arrangement of electrical property measurement ([0022]).
Regarding claim 7, Wang further teaches the method of claim 4, wherein the step of controlling the measurement device ([0037]), by executing the measurement program ([0037]), to measure the first part of the plurality of wafers according to the first recipe further comprises: controlling a thermal device of the measurement device, by executing the measurement program, to change a measurement environment temperature to the first measurement temperature ([0037]); and controlling the measurement device, by executing the measurement program, to measure the first part of the plurality of wafers according to the first recipe under the measurement environment temperature ([0037]).
Regarding claim 8, Wang further teaches the method of claim 2, wherein the second recipe includes a plurality of second parameters corresponding to the second part of the plurality of wafers, and the second recipe is different from the first recipe ([0032-0033]).
Regarding claim 9, Wang further teaches the method of claim 8, wherein the plurality of second parameters correspond to a second semiconductor device of the second part of the plurality of wafers ([0022]).
Regarding claim 10, Wang further teaches the method of claim 9, wherein the plurality of second parameters includes at least one of a second probe pattern of the probes of the measurement device ([0020, 0023, 0025, 0037]), a second measurement algorithm ([0020, 0023, 0025, 0037]) and a second measurement temperature ([0020, 0023, 0025, 0037]).
Regarding claim 11, Wang further teaches the method of claim 10, wherein the second probe pattern corresponds to contacts of the second semiconductor device ([0022]).
Regarding claim 12, Wang further teaches the method of claim 11, wherein the second measurement algorithm corresponds to a second arrangement of electrical property measurement ([0022]).
Regarding claim 13, Wang further teaches the method of claim 10, wherein the step of controlling the measurement device ([0037]), by executing the measurement program ([0037]), to measure the second part of the plurality of wafers according to the second recipe further comprises: controlling a thermal device of the measurement device, by executing the measurement program, to change a measurement environment temperature to a second temperature according to the second measurement temperature ([0037]); and controlling the measurement device, by executing the measurement program, to measure the second part of the plurality of wafers according to the second recipe under the measurement environment temperature ([0037]).
Regarding claim 14, Wang further teaches the method of claim 1, wherein, by executing the measurement program, the measurement device is controlled to automatically measure the second part of the plurality of wafers according to the second recipe after measuring the first part of the plurality of wafers according to the first recipe ([0032-0033]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chung et al. US 2007/0038327 - Disclosed is a semiconductor processing apparatus for processing batches of wafers with variable numbers of wafer lots. The apparatus includes an operator interface server adapted to receive batch information for a track-in operation, an equipment management server adapted to store data used to process the batch of wafers, and a device interface server adapted to control a selected unit of processing equipment used to process the batch of wafers.
Ikeno et al. US 2006/0161284 - A substrate inspection apparatus includes a recipe preparation unit that batch-allocates a plurality of slots containing substrates of each type with a corresponding one of a plurality of original recipes to the each type, the plurality of original recipes corresponding to different types of substrates respectively, so as to prepare an actual recipe based on the plurality of original recipes, and to inspect the different types of substrates according to the actual recipe.
Choi US 2024/0085891 - A virtual metrology method for a wafer includes collecting log data including process path information of wafers manufactured in a semiconductor process; collecting measured values of sample wafers of which physical characteristics are measured in the semiconductor process, the sample wafers being a group of wafers selected from among the manufactured wafers; classifying measured values of the sample wafers according to process paths based on the process path information; calculating a moving average value of measured values classified for each process path.
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/RAUL J RIOS RUSSO/Examiner, Art Unit 2858
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