DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “42” has been used to designate both support structure and images. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are also objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 22 and 62. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
(a) “22” in paragraph 20 should probably be --122-- (37 CFR 1.84(p)(4)); and
(b) “24” in paragraph 20 should probably be --124-- (37 CFR 1.84(p)(4)).
Appropriate correction is required.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of pre-AIA 35 U.S.C. 112, second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 4 and 11 is/are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
IEEE 1149.1 is a standard that changes (e.g., IEEE 1149.1-2013) and thus it is unclear what criteria classifies an interface as “a JTAG interface”.
Claim(s) dependent on the claim(s) discussed above is/are also indefinite for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandy et al. (US 2010/0249884) in view of Altera Corporation (Enhanced Configuration (EPC) Devices Datasheet (May 2016), 32 pages), Microchip Technology Inc. (SST25WF040B data sheet (August 2018), pp. 1, 6, and 18), and Aswadhati (US 9,250,687).
In regard to claim 1, Chandy et al. disclose a controller of an X-ray detector, comprising:
(a) a processor configured to execute instructions for operation of the X-ray detector (e.g., “… computer 14 is used to control an x-ray C-arm, not shown in FIG.1, of the multi-purpose system 10, through which the digital medical image data can be obtained …” in paragraph 48);
(b) a distributed memory communicatively coupled to the processor comprising a first memory and a second (Nth) memory, the first memory physically distinct from the second (Nth) memory (e.g., “… also possible to store on the file server several hard disk images of … hard disk … 24 …” in paragraph 56), wherein the first memory includes a loader including instructions to startup the X-ray detector (e.g., “… Stored on … hard disk … 24 … in a partition … 34 … is the file system with the operating system it contains and the other software it contains …” in paragraph 54).
While Chandy et al. also disclose (paragraph 53) that “… Instead of the central file server 30, it is also possible to provide for the files in the computer 12 to be held in a storage device which is designed for that purpose or to make available another computer with storage capacity appropriate for holding the files …” , the controller of Chandy et al. lacks an explicit description of details of the “… storage …” such as flash storage. However, “… storage …” details are known to one of ordinary skill in the art (e.g., see “JTAG/ISP Interface” in Figure 1: EPC Device Block Diagram and “… EPC device is divided into two major blocks—a configuration controller and a flash memory … EPC device features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial-device chain, the EPC device features concurrent configuration and parallel configuration … external flash interface allows remote and local updates of system configuration data …” in the Function Description section of the EPC Datasheet, “… Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register … puts the device in the lowest power consumption mode … Exit the power-down state using the Release from Deep Power-Down or Read ID instruction. CE# must be driven low before sending the Release from Deep Power-Down command cycle (ABH), and then driving CE# high. The device will return to Standby mode and be ready for the next instruction after TSBR …” in sections 4.1.1 and 5.13 of the SST25WF040B data sheet, and “… compared to a traditional hard-drive based storage system of similar storage capacity, the flash-based storage system typically provides decreased latency, increased IOPS, decreased power and cooling requirements, decreased size, and higher reliability …” in the third column 2 paragraph of Aswadhati). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional storage (e.g., comprising details such as “flash-based storage system” using commercially available chips, in order to achieve “decreased latency, increased IOPS, decreased power and cooling requirements, decreased size, and higher reliability” “compared to a traditional hard-drive based storage system of similar storage capacity”) for the unspecified storage of Chandy et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional storage (e.g., comprising details such as a first flash memory and a second (Nth) flash memory) as the unspecified storage of Chandy et al.
In regard to claim 2 which is dependent on claim 1, Chandy et al. also disclose that the second (Nth) memory includes instructions used during operation of the X-ray detector (e.g., “… Stored on … hard disk … 24 … in a partition … 34 … is the file system with the operating system it contains and the other software it contains … also possible to store on the file server several hard disk images of … hard disk … 24 … After the multi-purpose system 10 is switched on, the operating system is loaded into a working store in each of the computers 12, 14, 16 which is already in working order and the computers 12, 14, 16 are thereby put on stand-by … requests from the file server 30 the hard disk image 38' which had been stored by the computer 18 … after a restart of the new computer 44 it makes available the same functions as did previously the computer 18. The integration of the new computer 44 into the multi-purpose system 10 is thereby completed …” in paragraphs 54, 56, 61, 64, and 66).
In regard to claim 3 which is dependent on claim 1, the controller of Chandy et al. lacks an explicit description of details of the “… storage …” such as the first flash memory is coupled to the processor via a write protected pin, and wherein the first flash memory is configured to be de-energized after start-up. However, “… storage …” details are known to one of ordinary skill in the art (e.g., see “JTAG/ISP Interface” in Figure 1: EPC Device Block Diagram and “… EPC device is divided into two major blocks—a configuration controller and a flash memory … EPC device features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial-device chain, the EPC device features concurrent configuration and parallel configuration … external flash interface allows remote and local updates of system configuration data …” in the Function Description section of the EPC Datasheet, “… Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register … puts the device in the lowest power consumption mode … Exit the power-down state using the Release from Deep Power-Down or Read ID instruction. CE# must be driven low before sending the Release from Deep Power-Down command cycle (ABH), and then driving CE# high. The device will return to Standby mode and be ready for the next instruction after TSBR …” in sections 4.1.1 and 5.13 of the SST25WF040B data sheet, and “… compared to a traditional hard-drive based storage system of similar storage capacity, the flash-based storage system typically provides decreased latency, increased IOPS, decreased power and cooling requirements, decreased size, and higher reliability …” in the third column 2 paragraph of Aswadhati). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional storage (e.g., comprising details such as “flash-based storage system” using commercially available chips, in order to achieve a “lock-down function” with “power-down state” for “lowest power consumption mode”) for the unspecified storage of Chandy et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional storage (e.g., comprising details such as the first flash memory is coupled to the processor via a write protected pin, and wherein the first flash memory is configured to be de-energized after start-up of the X-ray detector) as the unspecified storage of Chandy et al.
In regard to claim 4 which is dependent on claim 1 in so far as understood, the controller of Chandy et al. lacks an explicit description of details of the “… storage …” such as the first flash memory is configured via an interface. However, “… storage …” details are known to one of ordinary skill in the art (e.g., see “JTAG/ISP Interface” in Figure 1: EPC Device Block Diagram and “… EPC device is divided into two major blocks—a configuration controller and a flash memory … EPC device features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial-device chain, the EPC device features concurrent configuration and parallel configuration … external flash interface allows remote and local updates of system configuration data …” in the Function Description section of the EPC Datasheet, “… Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register … puts the device in the lowest power consumption mode … Exit the power-down state using the Release from Deep Power-Down or Read ID instruction. CE# must be driven low before sending the Release from Deep Power-Down command cycle (ABH), and then driving CE# high. The device will return to Standby mode and be ready for the next instruction after TSBR …” in sections 4.1.1 and 5.13 of the SST25WF040B data sheet, and “… compared to a traditional hard-drive based storage system of similar storage capacity, the flash-based storage system typically provides decreased latency, increased IOPS, decreased power and cooling requirements, decreased size, and higher reliability …” in the third column 2 paragraph of Aswadhati). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional storage (e.g., comprising details such as “JTAG/ISP Interface” using commercially available chips, in order to achieve “lowest power consumption mode”) for the unspecified storage of Chandy et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional storage (e.g., comprising details such as the first flash memory is configured via an interface) as the unspecified storage of Chandy et al.
In regard to claim 5 which is dependent on claim 1, Chandy et al. also disclose that the first memory and second (Nth) memory are communicatively coupled to the processor via an external host configured to send instructions to the processor (e.g., “… computers 12, 14, 16, 18 are linked together to form a local area network (LAN). For this purpose they are connected to a common network facility 20 … control instructions are conveyed from the computer 12 to the other computers 14, 16, 18 … control instructions are transmitted from the computer 18 to the computer 14 … Also connected to the network facility 20 is a central file server 30 …” in paragraph 46, 50, and 53).
In regard to claim 6 which is dependent on claim 5, Chandy et al. also disclose that the first memory and second memory each include a plurality of copies of the loader (e.g., “… also possible to store on the file server several hard disk images of … hard disk … 24 …” in paragraph 56). Alternatively it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that the loader each included on the “several hard disk images” on both the first and second memories as automatic backup.
In regard to claim 7 which is dependent on claim 1, Chandy et al. also disclose that the distributed memory is non-volatile (e.g., “… also possible to store on the file server several hard disk images of … hard disk … 24 …” in paragraph 56). the controller of Chandy et al. lacks an explicit description of details of the “… storage …” such as an interface configured to communicatively couple an external processor to the distributed flash memory. However, “… storage …” details are known to one of ordinary skill in the art (e.g., see “JTAG/ISP Interface” in Figure 1: EPC Device Block Diagram and “… EPC device is divided into two major blocks—a configuration controller and a flash memory … EPC device features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial-device chain, the EPC device features concurrent configuration and parallel configuration … external flash interface allows remote and local updates of system configuration data …” in the Function Description section of the EPC Datasheet, “… Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register … puts the device in the lowest power consumption mode … Exit the power-down state using the Release from Deep Power-Down or Read ID instruction. CE# must be driven low before sending the Release from Deep Power-Down command cycle (ABH), and then driving CE# high. The device will return to Standby mode and be ready for the next instruction after TSBR …” in sections 4.1.1 and 5.13 of the SST25WF040B data sheet, and “… compared to a traditional hard-drive based storage system of similar storage capacity, the flash-based storage system typically provides decreased latency, increased IOPS, decreased power and cooling requirements, decreased size, and higher reliability …” in the third column 2 paragraph of Aswadhati). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional storage (e.g., comprising details such as “JTAG/ISP Interface” using commercially available chips, in order to achieve “lowest power consumption mode”) for the unspecified storage of Chandy et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional storage (e.g., comprising details such as an interface configured to communicatively couple an external processor to the distributed flash memory) as the unspecified storage of Chandy et al.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandy et al. in view of Altera Corporation, Microchip Technology Inc., and Aswadhati as applied to claim(s) 1 above, and further in view of Staver et al. (US 2003/0040820).
In regard to claims 8 and 9 which are dependent on claim 1, the controller of Chandy et al. lacks an explicit description of details of the “… storage …” such as the first flash memory is positioned on a first electrical board, and wherein the second (Nth) flash memory and the processor are positioned on a second electrical board, wherein the first electrical board is coupled to the second electrical board via two line drivers and the first electrical board is configured to be replaceable without replacing the second electrical board. However, “… storage …” details are known to one of ordinary skill in the art (e.g., “… EEPROM 530, 532 EPC-2 Altera … To facilitate test and debug, as well as for firmware updates in the field, DAP 372 and EP 374 are configurable through programmable memory unit 329. Programmable memory unit 329 includes DAP eeprom unit 532 and EP eeprom unit 530. Alternatively, DAP 372 and EP 374 are programmable JTAG ports JTAG1 542 and JTAG2 544. In typical operation, power is applied to DFN 304 when host computer 114 is first turned on. At this stage each of DAP 372 and EP 374 boot from their respective eeproms and therefore become operational by loading the data from the respective eeprom. FIG. 27 illustrates configuration circuitry on DFN 304. Each of DAP 372 and EP 374 has an associated eeprom unit comprised of two EPC2 chips that are daisy-chained to provide storage for programming. One eeprom unit per each of DAP 372 and EP 374 is shown for simplicity. Each EPC2 chip is a socketed 20 pin PLCC package, which is easily removed for reprogramming. As illustrated, configuration, i.e. loading data, is in passive serial mode in which a single line provides serial data to configure the devices … Daughter boards, with bus transceivers on them, provide high speed monitoring of signals on these lines without significantly loading them. These buses are used when testing EP 374 and DAP 372, which are FPGA devices and therefore not probed directly …” in paragraphs 160, 181, and 258 of Staver et al.). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional storage (e.g., comprising details such as “Daughter boards”, in order achieve “testing EP 374 and DAP 372”) for the unspecified storage of Chandy et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional storage (e.g., comprising details such as the first flash memory is positioned on a first electrical board, and wherein the second (Nth) flash memory and the processor are positioned on a second electrical board, wherein the first electrical board is coupled to the second electrical board via two line drivers and the first electrical board is configured to be replaceable without replacing the second electrical board) as the unspecified storage of Chandy et al.
Claim(s) 10, 12, 14, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandy et al. (US 2010/0249884) in view of Spiegel et al. (US 6,711,675).
In regard to claim 10, Chandy et al. disclose a method for operating a controller of an X-ray detector, comprising:
(a) starting up the X-ray detector via instructions included on a first loader stored on a first memory and coupled to a processor of the X-ray detector (e.g., “… computer 14 is used to control an x-ray C-arm … through which the digital medical image data can be obtained … software, including the operating system, which is stored on a hard disk … 24 … represents data which defines the way in which the computers … 14 … work …” in paragraphs 48 and 52); and
(b) in response to failed startup of the X-ray detector, starting up the X-ray detector with a second loader (e.g., “… After the multi-purpose system 10 is switched on, the operating system is loaded into a working store in each of the computers 12, 14, 16 which is already in working order and the computers 12, 14, 16 are thereby put on stand-by … requests from the file server 30 the hard disk image 38' which had been stored by the computer 18 … after a restart of the new computer 44 it makes available the same functions as did previously the computer 18. The integration of the new computer 44 into the multi-purpose system 10 is thereby completed …” in paragraphs 61, 64, and 66).
While Chandy et al. also disclose (paragraph 181) that “… typical operation, power is applied to DFN 304 when host computer 114 is first turned on. At this stage each of DAP 372 and EP 374 boot from their respective eeproms and therefore become operational by loading the data from the respective eeprom …”, the method of Chandy et al. lacks an explicit description of details of the “… boot …” such as locking the first flash memory of the controller in response to successful startup of the X-ray detector. However, “… boot …” details are known to one of ordinary skill in the art (e.g., see “… supplements the conventional boot sequence by introducing one or more groups of protected instructions into the sequence that are protected from tampering themselves … Firmware hub (FWH) 12 is a nonvolatile memory block containing instructions (code) that control and validate the boot sequence … Lock down is a process of stabilizing a block of code by preventing further write access to that code. This feature is dynamically available in the flash memory typically used for FWH 12 …” in column 2 of Spiegel et al.). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional boot sequence (e.g., comprising details such as “supplements the conventional boot sequence”, in order to “preventing further write access to that code. This feature is dynamically available in the flash memory typically used” so as to be “protected from tampering”) for the unspecified boot sequence of Chandy et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional boot sequence (e.g., comprising details such as in response to successful startup of the X-ray detector, locking the first flash memory of the controller) as the unspecified boot sequence of Chandy et al.
In regard to claim 12 which is dependent on claim 10, Chandy et al. also disclose that the first flash memory includes the second loader, and starting up the X-ray detector with the second loader is instructed by an external host communicatively coupled to the processor (e.g., “… After the multi-purpose system 10 is switched on, the operating system is loaded into a working store in each of the computers 12, 14, 16 which is already in working order and the computers 12, 14, 16 are thereby put on stand-by … requests from the file server 30 the hard disk image 38' which had been stored by the computer 18 … after a restart of the new computer 44 it makes available the same functions as did previously the computer 18. The integration of the new computer 44 into the multi-purpose system 10 is thereby completed …” in paragraphs 61, 64, and 66).
In regard to claim 14 which is dependent on claim 10, Chandy et al. also disclose that the second loader is included on a second flash memory, physically separate from the first flash memory, and starting up the X-ray detector with the second loader is instructed by an external host communicatively coupled to the processor (e.g., “… After the multi-purpose system 10 is switched on, the operating system is loaded into a working store in each of the computers 12, 14, 16 which is already in working order and the computers 12, 14, 16 are thereby put on stand-by … requests from the file server 30 the hard disk image 38' which had been stored by the computer 18 … after a restart of the new computer 44 it makes available the same functions as did previously the computer 18. The integration of the new computer 44 into the multi-purpose system 10 is thereby completed …” in paragraphs 61, 64, and 66).
In regard to claim 16 which is dependent on claim 10, Chandy et al. also disclose that in response to failing to startup the X-ray detector with the second loader, replacing an electrical board of the X-ray detector, the electrical board including the first flash memory (e.g., “… After the multi-purpose system 10 is switched on, the operating system is loaded into a working store in each of the computers 12, 14, 16 which is already in working order and the computers 12, 14, 16 are thereby put on stand-by … requests from the file server 30 the hard disk image 38' which had been stored by the computer 18 … after a restart of the new computer 44 it makes available the same functions as did previously the computer 18. The integration of the new computer 44 into the multi-purpose system 10 is thereby completed …” in paragraphs 61, 64, and 66).
Claim(s) 11, 13, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandy et al. in view of Spiegel et al. as applied to claim(s) 10 and 12 above, and further in view of Altera Corporation (Enhanced Configuration (EPC) Devices Datasheet (May 2016), 32 pages) and Staver et al. (US 2003/0040820).
In regard to claim 11 which is dependent on claim 10 in so far as understood, the method of Chandy et al. lacks an explicit description of details of the “… storage …” such as the controller is configured in an active serial configuration and booting the X-ray detector with the second loader includes replacing the first loader with the second loader via an interface. However, “… storage …” details are known to one of ordinary skill in the art (e.g., see “JTAG/ISP Interface” in Figure 1: EPC Device Block Diagram and “… EPC device is divided into two major blocks—a configuration controller and a flash memory … EPC device features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial-device chain, the EPC device features concurrent configuration and parallel configuration … external flash interface allows remote and local updates of system configuration data …” in the Function Description section of the EPC Datasheet and “… In typical operation, power is applied to DFN 304 when host computer 114 is first turned on. At this stage each of DAP 372 and EP 374 boot from their respective eeproms and therefore become operational by loading the data from the respective eeprom … loads the initial boot sequence instructions for execution by control unit 570 upon reset or initial application of power to detector framing node 304. According to an embodiment of the present invention, the initial boot sequence instructions are updated by communicating update instructions from host computer 114 through the computer communication interface 382 and into detector framing node memory unit 380. The update instructions are then communicated from detector framing node memory unit 380 to the programmable memory unit 529. The JTAG loop 545 communicates the update instructions from local bus 384 and programmable memory unit 529 … jumpers are provided to selectively disable reboot of DAP 372 or EP 374 in order to help debug problems during configuration or due to specific devices … firmware is optionally updated to a different version. For convenience, these updates are performed directly without opening host computer 114 and swapping eeprom devices for a later revision. The capability for in-system programming of the eeprom units is supported through respective JTAG ports as mentioned above. DFN 304 allows host computer 114 to access the JTAGl 542 or JTAG2 544 directly over computer communication bus 302 without using the Byte Blaster cable and MaxPlusll software …” in paragraphs 181-183, and 186 of Staver et al.). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional storage (e.g., comprising details such as “JTAG/ISP Interface” using commercially available chips with “traditional passive serial (PS) configuration scheme for a single device or a serial-device chain, the EPC device features concurrent configuration and parallel configuration”, in order to achieve “remote and local updates of system configuration data” such as “firmware is optionally updated to a different version”) for the unspecified storage of Chandy et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional storage (e.g., comprising details such as the controller is configured in an active serial configuration and booting the X-ray detector with the second loader includes replacing the first loader with the second loader via an interface) as the unspecified storage of Chandy et al.
In regard to claim 13 which is dependent on claim 12, the method of Chandy et al. lacks an explicit description of details of the “… storage …” such as in response to starting up the X-ray detector with the second loader, indicating via the external host the second loader is non-corrupted for future startups. However, “… storage …” details are known to one of ordinary skill in the art (e.g., see “JTAG/ISP Interface” in Figure 1: EPC Device Block Diagram and “… EPC device is divided into two major blocks—a configuration controller and a flash memory … EPC device features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial-device chain, the EPC device features concurrent configuration and parallel configuration … external flash interface allows remote and local updates of system configuration data …” in the Function Description section of the EPC Datasheet and “… In typical operation, power is applied to DFN 304 when host computer 114 is first turned on. At this stage each of DAP 372 and EP 374 boot from their respective eeproms and therefore become operational by loading the data from the respective eeprom … loads the initial boot sequence instructions for execution by control unit 570 upon reset or initial application of power to detector framing node 304. According to an embodiment of the present invention, the initial boot sequence instructions are updated by communicating update instructions from host computer 114 through the computer communication interface 382 and into detector framing node memory unit 380. The update instructions are then communicated from detector framing node memory unit 380 to the programmable memory unit 529. The JTAG loop 545 communicates the update instructions from local bus 384 and programmable memory unit 529 … jumpers are provided to selectively disable reboot of DAP 372 or EP 374 in order to help debug problems during configuration or due to specific devices … firmware is optionally updated to a different version. For convenience, these updates are performed directly without opening host computer 114 and swapping eeprom devices for a later revision. The capability for in-system programming of the eeprom units is supported through respective JTAG ports as mentioned above. DFN 304 allows host computer 114 to access the JTAGl 542 or JTAG2 544 directly over computer communication bus 302 without using the Byte Blaster cable and MaxPlusll software …” in paragraphs 181-183, and 186 of Staver et al.). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional storage (e.g., comprising details such as “jumpers are provided to selectively disable reboot”, in order to achieve “remote and local updates of system configuration data” such as “firmware is optionally updated to a different version”) for the unspecified storage of Chandy et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional storage (e.g., comprising details such as in response to starting up the X-ray detector with the second loader, indicating via the external host the second loader is non-corrupted for future startups) as the unspecified storage of Chandy et al.
In regard to claim 15 which is dependent on claim 10, the method of Chandy et al. lacks an explicit description of details of the “… storage …” such as locking the first flash memory includes de-energizing the first flash memory and/or preventing the processor from accessing the first flash memory. However, “… storage …” details are known to one of ordinary skill in the art (e.g., see “JTAG/ISP Interface” in Figure 1: EPC Device Block Diagram and “… EPC device is divided into two major blocks—a configuration controller and a flash memory … EPC device features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial-device chain, the EPC device features concurrent configuration and parallel configuration … external flash interface allows remote and local updates of system configuration data …” in the Function Description section of the EPC Datasheet and “… In typical operation, power is applied to DFN 304 when host computer 114 is first turned on. At this stage each of DAP 372 and EP 374 boot from their respective eeproms and therefore become operational by loading the data from the respective eeprom … loads the initial boot sequence instructions for execution by control unit 570 upon reset or initial application of power to detector framing node 304. According to an embodiment of the present invention, the initial boot sequence instructions are updated by communicating update instructions from host computer 114 through the computer communication interface 382 and into detector framing node memory unit 380. The update instructions are then communicated from detector framing node memory unit 380 to the programmable memory unit 529. The JTAG loop 545 communicates the update instructions from local bus 384 and programmable memory unit 529 … jumpers are provided to selectively disable reboot of DAP 372 or EP 374 in order to help debug problems during configuration or due to specific devices … firmware is optionally updated to a different version. For convenience, these updates are performed directly without opening host computer 114 and swapping eeprom devices for a later revision. The capability for in-system programming of the eeprom units is supported through respective JTAG ports as mentioned above. DFN 304 allows host computer 114 to access the JTAGl 542 or JTAG2 544 directly over computer communication bus 302 without using the Byte Blaster cable and MaxPlusll software …” in paragraphs 181-183, and 186 of Staver et al.). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional storage (e.g., comprising details such as “jumpers are provided to selectively disable reboot”, in order to achieve “remote and local updates of system configuration data” such as “firmware is optionally updated to a different version”) for the unspecified storage of Chandy et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional storage (e.g., comprising details such as locking the first flash memory includes de-energizing the first flash memory and/or preventing the processor from accessing the first flash memory) as the unspecified storage of Chandy et al.
Claim(s) 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Staver et al. (US 2003/0040820) in view of Spiegel et al. (US 6,711,675).
In regard to claim 17, Staver et al. disclose a system configured to control an X-ray detector, comprising:
(a) a field programmable gate array (FPGA) (e.g., “… two FPGAs control the flow of data through the card. The EP 374 contains a sequencer, which orchestrates detector and x-ray event instructions in real time. EP 374 also contains a command interpreter which communicates with host computer 114 …” in paragraph 156);
(b) a first flash memory communicatively coupled to the FPGA, the first flash memory comprising a loader (e.g., “… EEPROM 530, 532 EPC-2 Altera … To facilitate test and debug, as well as for firmware updates in the field, DAP 372 and EP 374 are configurable through programmable memory unit 329. Programmable memory unit 329 includes DAP eeprom unit 532 and EP eeprom unit 530. Alternatively, DAP 372 and EP 374 are programmable JTAG ports JTAG1 542 and JTAG2 544. In typical operation, power is applied to DFN 304 when host computer 114 is first turned on. At this stage each of DAP 372 and EP 374 boot from their respective eeproms and therefore become operational by loading the data from the respective eeprom. FIG. 27 illustrates configuration circuitry on DFN 304. Each of DAP 372 and EP 374 has an associated eeprom unit comprised of two EPC2 chips that are daisy-chained to provide storage for programming. One eeprom unit per each of DAP 372 and EP 374 is shown for simplicity. Each EPC2 chip is a socketed 20 pin PLCC package, which is easily removed for reprogramming. As illustrated, configuration, i.e. loading data, is in passive serial mode in which a single line provides serial data to configure the devices …” in paragraph 160 and 181); and
(c) a second (Nth) flash memory communicatively coupled to the FPGA (e.g., “… Each of DAP 372 and EP 374 has an associated eeprom unit comprised of two EPC2 chips that are daisy-chained …” in paragraph 160).
While Staver et al. also disclose (paragraph 181) that in “… typical operation, power is applied to DFN 304 when host computer 114 is first turned on. At this stage each of DAP 372 and EP 374 boot from their respective eeproms and therefore become operational by loading the data from the respective eeprom …”, the system of Staver et al. lacks an explicit description of details of the “… boot …” such as the FPGA includes instructions to lock the first flash memory after successful startup of the X-ray detector. However, “… boot …” details are known to one of ordinary skill in the art (e.g., see “… supplements the conventional boot sequence by introducing one or more groups of protected instructions into the sequence that are protected from tampering themselves … Firmware hub (FWH) 12 is a nonvolatile memory block containing instructions (code) that control and validate the boot sequence … Lock down is a process of stabilizing a block of code by preventing further write access to that code. This feature is dynamically available in the flash memory typically used for FWH 12 …” in column 2 of Spiegel et al.). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional boot sequence (e.g., comprising details such as “supplements the conventional boot sequence”, in order to “preventing further write access to that code. This feature is dynamically available in the flash memory typically used” so as to be “protected from tampering”) for the unspecified boot sequence of Staver et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional boot sequence (e.g., comprising details such as the FPGA includes instructions to lock the first flash memory after successful startup of the X-ray detector) as the unspecified boot sequence of Staver et al.
In regard to claim 19 which is dependent on claim 17, Staver et al. also disclose that the first flash memory and second (Nth) flash memory are coupled to the FPGA in a passive serial or fast passive parallel configuration (e.g., “… Each EPC2 chip is a socketed 20 pin PLCC package, which is easily removed for reprogramming. As illustrated, configuration, i.e. loading data, is in passive serial mode in which a single line provides serial data to configure the devices …” in paragraph 181).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Staver et al. in view of Spiegel et al. as applied to claim(s) 17 above, and further in view of Altera Corporation (Enhanced Configuration (EPC) Devices Datasheet (May 2016), 32 pages).
In regard to claim 18 which is dependent on claim 17, the system of Staver et al. lacks an explicit description of details of the “… EPC-2 Altera …” such as the first flash memory and second (Nth) flash memory are coupled to the FPGA in an active serial configuration. However, “… EPC-2 Altera …” details are known to one of ordinary skill in the art (e.g., see “JTAG/ISP Interface” in Figure 1: EPC Device Block Diagram and “… EPC device is divided into two major blocks—a configuration controller and a flash memory … EPC device features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial-device chain, the EPC device features concurrent configuration and parallel configuration … external flash interface allows remote and local updates of system configuration data …” in the Function Description section of the EPC Datasheet). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional flash memory configuration (e.g., comprising details such as “configuration controller”, in order to achieve “remote and local updates”) for the flash memory configuration of Staver et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional flash memory configuration (e.g., comprising details such as the first flash memory and second (Nth) flash memory are coupled to the FPGA in an active serial configuration) as the flash memory configuration of Staver et al.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Staver et al. in view of Spiegel et al. as applied to claim(s) 19 above, and further in view of Chandy et al. (US 2010/0249884).
In regard to claim 20 which is dependent on claim 19, while Staver et al. also disclose (paragraph 128) that “… Second PCI sub bus 346 interconnects with disk archive 308 by way of small computer systems interface ("SCSI") 348 …”, the system of Staver et al. lacks an explicit description of details of the “… disk archive …” such as an external redundant non-volatile memory device including the loader and coupled to the FPGA via an external host. However, “… disk archive …” details are known to one of ordinary skill in the art (e.g., see “… central file server 30, e.g. an NAS (Network Attached Storage). In the file server are held files which are used by the computers 12, 14, 16, 18 which must not be lost even if, for example, one of the hard disks 22, 24, 26, 28 should become functionally incompetent. Instead of the central file server 30, it is also possible to provide for the files in the computer 12 to be held in a storage device which is designed for that purpose or to make available another computer with storage capacity appropriate for holding the files … stored as a hard disk image …” in paragraphs 53 and 54 of Chandy et al.). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional file server (e.g., comprising details such as “stored as a hard disk image”, in order to prevent “lost” if “one of the hard disks 22, 24, 26, 28 should become functionally incompetent”) for the unspecified file server of Staver et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional file server (e.g., comprising details such as an external redundant non-volatile memory device including the loader and coupled to the FPGA via an external host) as the unspecified file server of Staver et al.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 8,916,844 teaches a X-ray cassette.
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/SL/
Examiner, Art Unit 2884
/UZMA ALAM/Supervisory Patent Examiner, Art Unit 2884