DETAILED ACTION
The Amendment filed January 12, 2025 has been entered. Claims 1-21 are pending. Claim 15 has been cancelled. Claim 21 has been added. Claims 1, 14 and 20 are independent.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-9, 14, 16-18 and 20-21 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Conte et al. (US 2022/0044099) in view of Chuang et al. (US 2020/0194662).
Regarding independent claims 1, 14 and 20, Conte et al. teach a circuit comprising:
a memory array (see FIG. 4 along with FIG. 2);
a mimic column (FIG. 4: BL column; and para. 0134: … emulating the elements in the array; i.e., interpreted as a mimic column based on the explanation in the Applicant’s specification para. 0015, a mimic column) along a periphery (DEC, DAC) of the memory array and comprising mimic cells (G11 and RB1 pair through Gi4 and RB2 pair), each mimic cell of the mimic cells having a respective electrical path through the respective mimic cell (see FIG. 4 and accompanying disclosure);
a mimic resistor (FIG. 4: RCWL) in the respective electrical paths through the mimic cells (G11 and RB1 pair through Gi4 and RB2 pair); and
a calibration circuit (FIG. 4: OUTCVRT, along with FIGS. 6-7) configured to calibrate a voltage for writing a memory cell in the memory array (para. 0137: the calibration process comprises emulating the output voltage VOUT resulting … from the reference voltage signal V0 biasing the reference phase-change resistive memory cell PCM0 … and comprises comparing CMP the emulated output value VOUT with a reference output value VREF …), the calibration circuit being electrically connected to the mimic resistor (FIG. 4: RCWL).
Conte’s a calibration circuity does not explicitly disclose calibrate a voltage for writing a memory cell in the memory array.
Chuang et al. teach the deficiencies in e.g., para. 0019: … the storage device to obtain the calibrated voltages for accessing the JTM devices; and para. 0024: … the calibrated voltages used to access (write …) the MTJ cells …
Conte and Chuang are analogous art because they both are directed to resistive memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Conte with the specified features of Chuang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Chuang et al. to the teaching of Conte et al. such that a memory, as taught by Conte et al., utilizes voltage calibration for memory writing, as taught by Chuang et al., for the purpose of enhancing memory operations such as write and read operations.
Regarding claim 2, Conte et al. and Chuang et al., as combined, teach the limitations of claim 1.
Conte and Chaung et al. do not explicitly disclose a dummy column between the memory array and the mimic column.
However, the placement of columns in a memory array is a well-known technology for a type of memory structure for its purpose.
For support, of the above asserted facts, see for example, Nii et al. (US 2003/0202412), e.g., FIG. 14; 23-21e comprises peripheral column, 21f comprises dummy column and 20 comprises memory array.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize column placement in a memory array because these conventional technology are well established in the art of the memory devices.
Regarding claim 3, Conte et al. and Chuang et al., as combined, teach the limitations of claim 1.
Chuang et al. further teach a first number of word lines, wherein: the memory array includes memory cells arranged in the first number of rows and a second number of columns; the mimic column includes the first number of mimic cells; and a word line of the word lines is electrically connected to memory cells of the memory array and a mimic cell of the mimic column in a respective row (see e.g., FIG. 2 and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Chung et al. for the same purpose of performing enhanced memory operations.
Regarding claims 4-6, Conte et al. and Chuang et al., as combined, teach the limitations of claim 3.
Chuang et al. further teach the second number of source lines (FIG. 2: bold lines) and the second number of bit lines (lines coupled to mtjs), wherein a source line of the second number of the source lines is electrically connected to memory cells of the memory array in a respective column, and a bit line of the second number of the bit lines is electrically connected to the memory cells of the memory array in the respective column; and a mimic source line and a mimic bit line, wherein the mimic source line is electrically connected to the mimic cells of the mimic column, and the mimic bit line is electrically connected to the mimic cells of the mimic column; the mimic resistor is in the mimic bit line; and the mimic resistor is in the mimic source line (see e.g., FIG. 2 and accompanying disclosure).
Regarding claims 7 and 16, Conte et al. and Chuang et al., as combined, teach the limitations of claims 1 and 15, respectively.
Chuang et al. further teach the memory array includes memory cells, the memory cells including the memory cell, the memory cell including: a first access transistor having a first source/drain node, a second source/drain node, and a first gate node, the first source/drain node being electrically connected to a source line of a column of the memory array in which the memory cell is disposed, the first gate node being electrically connected to a word line of a row of the memory array in which the memory cell is disposed; and a magnetic tunnel junction (MTJ) having a first terminal and a second terminal, the first terminal being electrically connected to the second source/drain node, the second terminal being electrically connected to a bit line of the column of the memory array in which the memory cell is disposed; and the mimic column includes mimic cells, a mimic cell of the mimic cells including a second access transistor having a third source/drain node, a fourth source/drain node, and a second gate node, the third source/drain node being electrically connected to a mimic source line, the second gate node being electrically connected to the word line, the fourth source/drain node being electrically connected to a mimic bit line (see e.g., FIG. 2 along with FIGS. 8B-D and accompanying disclosure).
Regarding claims 8 and 17, Conte et al. and Chuang et al., as combined, teach the limitations of claims 1 and 16, respectively.
Chuang et al. further teach the voltage that is calibrated by the calibration circuit is applied to a source line (FIG. 2: bold line) or a bit line (102_m line), the memory cell in the memory array being electrically connected between the source line and the bit line (see e.g., FIG. 2 and accompanying disclosure).
Regarding claims 9 and 18, Conte et al. and Chuang et al., as combined, teach the limitations of claims 1 and 16, respectively.
Chuang et al. further teach the voltage that is calibrated by the calibration circuit is applied to a word line (FIG. 2: 106_m gate line), the memory cell in the memory array being electrically connected to the word line (see e.g., FIG. 2 and accompanying disclosure).
Regarding claim 21, Conte et al. and Chuang et al., as combined, teach the limitations of claim 1.
Conte et al. further teach each mimic cell of the mimic cells is a same type of cell as the memory cell of the memory array except having a short circuit corresponding to a memory element of the memory cell (see FIG. 4 and accompanying disclosure, i.e., does not include a short circuit).
Allowable Subject Matter
Claims 10-13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s amendment filed 01/12/2026, with respect to the rejection(s) of claims 1-20 under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
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