Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/26/2024,01/06/2025, and 12/12/2025 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, and 7-9 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee; Jin-Yuan et al. US 2023/0363182 A1.
Lee: Full text, particularly Figs 28 and 31A and paragraphs [0040], [0041], [0250], [0256], [0344], [0390], [0391] of the Description] discloses a semiconductor device (301), comprising: a first die (200) comprising: a first substrate, a plurality of non-planar MOSFET devices (paragraph [0256] of the Description) formed on the first substrate, and a plurality of first contact pads (34) electrically connected to the non-planar MOSFET devices; a second die (411) comprising: a second substrate, a plurality of planar MOSFET devices (paragraph [0041] of the Description) formed on the second substrate, and a plurality of second contact pads (34) electrically connected to the planar MOSFET devices; an insulation material (92/42) formed on the first and second substrates; a plurality of contacts (570) formed on the insulation material; and a plurality of paths of conductive material (27) extending through the insulation material, and electrically connected to respective ones of the contacts, the first contact pads (34) and the second contact pads (34).
Regarding Claim 2, [Figs. 28 and 31A] discloses a first plurality of the paths of conductive material (27) are electrically connected to selected ones of the contacts (570) and selected ones of the first contact pads (34); a second plurality of the paths of conductive material are electrically connected to selected ones of the contacts and selected ones of the second contact pads; and a third plurality of the paths of conductive material are electrically connected to selected ones of the first contact pads and selected ones of the second contact pads.
Regarding claim 3, [paragraphs [0041], [0344] of the Description] discloses that the second die does not include any non-planar MOSFET devices.
Regarding Claim 7, [paragraph [0265] of the Description] discloses that the planar MOSFET devices formed on the second substrate include a plurality of logic devices, wherein respective ones of the logic devices comprises: a source region and a drain region formed in the second substrate (411), with a channel region of the second substrate extending between the source region and the drain region and extending along a planar upper surface of the second substrate; and a conductive gate disposed over and insulated from the channel region.
Regarding Claim 8, [paragraph [0041] of the Description] discloses that .the non-planar MOSFET devices formed on the first substrate include a plurality of FinFET logic devices, wherein respective ones of the FinFET logic devices comprises: a fin of semiconductor material extending from a surface of the first substrate, wherein the fin includes a plurality of side surfaces terminating in a top surface; a source region and a drain region formed in the fin of semiconductor material, with a channel region extending between the source region and the drain region, wherein the channel region extends along the side surfaces and the top surface of the fin of semiconductor material; and a conductive gate that wraps around and is insulated from the channel region of the top surface and the side surfaces of the fin of semiconductor material.
Regarding Claim 9, [paragraph [0041] of the Description] discloses that the non-planar MOSFET devices formed on the first substrate include a plurality of gate-all-around logic devices, wherein respective ones of the gate-all-around logic devices comprises: a conductive gate disposed over and insulated from the first substrate; a wire of semiconductor material extending through the conductive gate; and a source region and a drain region formed in the wire of semiconductor material, with a channel region extending between the source region and the drain region, wherein the channel region extends through the conductive gate
Claim(s)10, 11, 13, 17-24 and 28-30, is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yang; Ping-Jung et al., US 20220384326 A1
Yang discloses [Full text, particularly Figs. 12A, 12B, 13A and 13B and paragraphs [0185], [0200], [0211]-[0225], and [0230] of the Description] discloses a semiconductor device (190), comprising: a first die (399) comprising: a first substrate, a plurality of non-planar MOSFET devices (paragraph [0224] of the Description) formed on the first substrate, and a plurality of first contact pads (6a) electrically connected to the non-planar MOSFET devices; a second die (159 or 397) comprising: a second substrate, a plurality of planar MOSFET devices (paragraph [0224] of the Description) formed on the second substrate, and a plurality of second contact pads (6a) electrically connected to the planar MOSFET devices; wherein selected ones of the first contact pads are physically bonded to selected ones of the second contact pads; and a conductive via or a wire (467/907) in electrical contact with one of the first or second contact pads.
Regarding Claim 11, [Figs. 13A and 13B] discloses a via insulation material (901/910) disposed over the one of the first or second contact pads; and the conductive via (467) is in electrical contact (907) with the one of the first or second contact pads, wherein the conductive via extends through the insulation material.
Regarding Claim 13, [paragraph [0224] of the Description] discloses that the second die does not include any non-planar MOSFET devices.
Regarding Claim 17, [paragraph [0230] of the Description] discloses that the planar MOSFET devices formed on the second substrate include a plurality of logic devices (397), wherein respective ones of the logic devices comprises: a source region and a drain region formed in the second substrate, with a channel region of the second substrate extending between the source region and the drain region and extending along a planar upper surface of the second substrate; and a conductive gate disposed over and insulated from the channel region.
Regarding Claim 18, [paragraph [0224] of the Description] discloses that the non-planar MOSFET devices formed on the first substrate include FinFET logic devices, wherein respective ones of the FinFET logic devices comprises: a fin of semiconductor material extending from a surface of the first substrate, wherein the fin includes a plurality of side surfaces terminating in a top surface; a source region and a drain region formed in the fin of semiconductor material, with a channel region extending between the source region and the drain region, wherein the channel region extends along the side surfaces and the top surface of the fin of semiconductor material; and a conductive gate that wraps around and is insulated from the channel region of the top surface and the side surfaces of the fin of semiconductor material.
Regarding Claim 19, [paragraph [0224] of the Description] discloses that the non-planar MOSFET devices formed on the first substrate include a plurality of gate-all-around logic devices, wherein respective ones of the gate-all-around logic devices comprises: a conductive gate disposed over and insulated from the first substrate; a wire of semiconductor material extending through the conductive gate; and a source region and a drain region formed in the wire of semiconductor material, with a channel region extending between the source region and the drain region, wherein the channel region extends through the conductive gate.
Regarding Claim 20, [Full text, particularly Figs. 12A, 12B, 13A and 13B and paragraphs [0185], [0200], [0211]-[0225], [0230] of the Description] discloses a semiconductor device (190), comprising: a first die (399) comprising: a first substrate, a plurality of non-planar MOSFET devices (paragraph [0224] of the Description) formed on the first substrate, and a plurality of first contact pads (6a) electrically connected to the non-planar MOSFET devices; a second die (159 or 397) comprising: a second substrate, a plurality of planar MOSFET devices (paragraph [0224] of the Description) formed on the second substrate, and a plurality of second contact pads electrically connected to the planar MOSFET devices; wherein selected ones of the first contact pads are electrically connected to selected ones of the second contact pads (6a) by a plurality of conductive pillars (37/48, paragraph [0185] of the Description, and Fig. 12B); and a conductive via or a wire in electrical contact with one of the first or second contact pads.
Regarding Claim 21, [Figs. 13A and 13B] discloses a via insulation material (901/910) disposed over the one of the first or second contact pads; and the conductive via (467) is in electrical contact (907) with the one of the first or second contact pads, wherein the conductive via extends through the insulation material.
Regarding Claim 23, [Fig. 13B and paragraph [0215] of the Description] discloses a fill insulation material (169) disposed between the first and second substrates, wherein the conductive pillars (37) extend through the insulation material.
Regarding Claim 24, [paragraph [0224] of the Description] discloses that the second die does not include any non-planar MOSFET devices.
Regarding Claim 28, [paragraph [0230] of the Description] discloses that
the planar MOSFET devices formed on the second substrate include a plurality of logic devices (397), wherein respective ones of the logic devices comprises: a source region and a drain region formed in the second substrate, with a channel region of the second substrate extending between the source region and the drain region and extending along a planar upper surface of the second substrate; and a conductive gate disposed over and insulated from the channel region.
Regarding Claim 29, [paragraph [0224] of the Description] discloses that the non-planar MOSFET devices formed on the first substrate include FinFET logic devices, wherein respective ones of the FinFET logic devices comprises: a fin of semiconductor material extending from a surface of the first substrate, wherein the fin includes a plurality of side surfaces terminating in a top surface; a source region and a drain region formed in the fin of semiconductor material, with a channel region extending between the source region and the drain region, wherein the channel region extends along the side surfaces and the top surface of the fin of semiconductor material; and a conductive gate that wraps around and is insulated from the channel region of the top surface and the side surfaces of the fin of semiconductor material.
Regarding Claim 30, [paragraph [0224] of the Description] discloses that the non-planar MOSFET devices formed on the first substrate include a plurality of gate-all-around logic devices, wherein respective ones of the gate-all-around logic devices comprises: a conductive gate disposed over and insulated from the first substrate; a wire of semiconductor material extending through the conductive gate; and a source region and a drain region formed in the wire of semiconductor material, with a channel region extending between the source region and the drain region, wherein the channel region extends through the conductive gate.
Allowable Subject Matter
Claim 4-6, 12, 14-16, 22, and 25-27 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art references fail to teach:
. 4. The semiconductor device of claim 1, wherein the planar MOSFET devices formed on the second substrate include non-volatile memory cells, wherein respective ones of the non-volatile memory cells comprises:
a source region and a drain region formed in the second substrate, with a channel region of the second substrate extending between the source region and the drain region and extending along a planar upper surface of the second substrate;
a floating gate disposed over and insulated from a first portion of the channel region; and
a select gate disposed over and insulated from a second portion of the channel region.
12. The semiconductor device of claim 10, wherein the wire is in electrical contact with the one of the first or second contact pads.
14. The semiconductor device of claim 10, wherein the planar MOSFET devices formed on the second substrate include non-volatile memory cells, wherein respective ones of the non-volatile memory cells comprises:
a source region and a drain region formed in the second substrate, with a channel region of the second substrate extending between the source region and the drain region and extending along a planar upper surface of the second substrate;
a floating gate disposed over and insulated from a first portion of the channel region; and
a select gate disposed over and insulated from a second portion of the channel region.
22. The semiconductor device of claim 20, wherein the wire is in electrical contact with the one of the first or second contact pads.
25. The semiconductor device of claim 20, wherein the planar MOSFET devices formed on the second substrate include non-volatile memory cells, wherein respective ones of the non-volatile memory cells comprises:
a source region and a drain region formed in the second substrate, with a channel region of the second substrate extending between the source region and the drain region and extending along a planar upper surface of the second substrate;
a floating gate disposed over and insulated from a first portion of the channel region; and
a select gate disposed over and insulated from a second portion of the channel region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893
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